riscv/rocket-chip
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Cover all exceptions and interrupts

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This commit is contained in:
Andrew Waterman 2018-01-16 00:45:50 -08:00
parent 8799508b1f
commit d2399b6d0e
1 changed files with 16 additions and 14 deletions
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30
src/main/scala/rocket/CSR.scala
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@ -566,20 +566,22 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
} }
} }
for ( for (i <- 0 until supported_interrupts.getWidth) {
(cover_reg, cover_reg_label) <- List( val en = exception && (supported_interrupts & (BigInt(1) << i).U) =/= 0 && cause === (BigInt(1) << (xLen - 1)).U + i
(mCause, "MCAUSE"), val delegable = (delegable_interrupts & (BigInt(1) << i).U) =/= 0
(sCause, "SCAUSE") cover(en, s"INTERRUPT_M_$i")
); cover(en && delegable && delegate, s"INTERRUPT_S_$i")
(cover_cause_code, cover_cause_label) <- List( }
(Causes.user_ecall, "ECALL_USER"), for (i <- 0 until xLen) {
(Causes.supervisor_ecall, "ECALL_SUPERVISOR"), val supported_exceptions = 0x87e |
(Causes.hypervisor_ecall, "ECALL_HYPERVISOR"), (if (usingCompressed && !coreParams.misaWritable) 0 else 1) |
(Causes.machine_ecall, "ECALL_MACHINE") (if (usingUser) 0x100 else 0) |
) (if (usingVM) 0xb200 else 0)
) { if (((supported_exceptions >> i) & 1) != 0) {
cover((xcause_dest === cover_reg) && (cause === UInt(cover_cause_code)), val en = exception && cause === i
s"${cover_reg_label}_${cover_cause_label}") cover(en, s"EXCEPTION_M_$i")
cover(en && delegate, s"EXCEPTION_S_$i")
}
} }
when (insn_ret) { when (insn_ret) {