From d21ffa4dbaf6c4074266a005800f68f11c101111 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 28 Jul 2015 00:23:31 -0700 Subject: [PATCH] Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used --- Makefrag | 23 +++-------------------- README.md | 4 ++-- fsim/Makefile | 4 ++-- src/main/scala/Testing.scala | 2 +- vsim/Makefile | 4 ++-- vsim/Makefrag | 4 ++-- vsim/{Makefrag-sim => Makefrag-verilog} | 20 ++++++++++++++++++++ 7 files changed, 32 insertions(+), 29 deletions(-) rename vsim/{Makefrag-sim => Makefrag-verilog} (60%) diff --git a/Makefrag b/Makefrag index cb14afb3..3ecde4c2 100644 --- a/Makefrag +++ b/Makefrag @@ -4,12 +4,15 @@ $(error Please set environment variable RISCV. Please take a look at README) endif MODEL := Top +PROJECT := rocketchip CXX := g++ CXXFLAGS := -O1 SBT := java -Xmx2048M -Xss8M -XX:MaxPermSize=128M -jar sbt-launch.jar SHELL := /bin/bash +CHISEL_ARGS := $(MODEL) --W0W --backend $(BACKEND) --configInstance $(PROJECT).$(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir) + src_path = src/main/scala chisel_srcs = $(base_dir)/$(src_path)/*.scala $(base_dir)/rocket/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(base_dir)/zscale/$(src_path)/*.scala $(SRC_EXTENSION) @@ -21,26 +24,6 @@ endif timeout_cycles = 100000000 -#-------------------------------------------------------------------- -# Verilog Generation -#-------------------------------------------------------------------- - -$(generated_dir)/$(MODEL).$(CONFIG).v: $(chisel_srcs) $(generated_dir)/memdessertMemDessert.$(CONFIG).v - cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "run $(MODEL) --backend $(BACKEND) --targetDir $(generated_dir) --W0W --configDump --noInlineMem --configInstance rocketchip.$(CONFIG)" - cd $(generated_dir) && \ - if [ -a $(MODEL).$(CONFIG).conf ]; then \ - $(mem_gen) $(generated_dir)/$(MODEL).$(CONFIG).conf >> $(generated_dir)/$(MODEL).$(CONFIG).v; \ - fi - -$(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(MODEL).$(CONFIG).v - echo "\`ifndef CONST_VH" > $@ - echo "\`define CONST_VH" >> $@ - sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $(patsubst %.v,%.prm,$<) >> $@ - echo "\`endif // CONST_VH" >> $@ - -$(generated_dir)/memdessertMemDessert.$(CONFIG).v: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala - cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "run MemDessert --backend v --targetDir $(generated_dir) --W0W --moduleNamePrefix memdessert --configInstance rocketchip.$(CONFIG)" - #-------------------------------------------------------------------- # DRAMSim2 #-------------------------------------------------------------------- diff --git a/README.md b/README.md index 23193ba0..e29c6e2e 100644 --- a/README.md +++ b/README.md @@ -262,13 +262,13 @@ generated Rocket chip has passed all assembly tests and benchmarks! You can also run assembly tests and benchmarks separately: $ make -jN run-asm-tests - $ make -jN run-bmarks-tests + $ make -jN run-bmark-tests To generate vcd waveforms, you can run one of the following commands: $ make -jN run-debug $ make -jN run-asm-tests-debug - $ make -jN run-bmarks-tests-debug + $ make -jN run-bmark-tests-debug Or call out individual assembly tests or benchmarks: diff --git a/fsim/Makefile b/fsim/Makefile index 80a5767a..fe89bfa3 100644 --- a/fsim/Makefile +++ b/fsim/Makefile @@ -21,8 +21,8 @@ TB ?= rocketTestHarness include $(base_dir)/Makefrag include $(sim_dir)/Makefrag --include $(generated_dir)/Makefrag-tests.$(CONFIG) -include $(base_dir)/vsim/Makefrag-sim +-include $(generated_dir)/$(MODEL).$(CONFIG).d +include $(base_dir)/vsim/Makefrag-verilog all: $(simv) debug: $(simv_debug) diff --git a/src/main/scala/Testing.scala b/src/main/scala/Testing.scala index 37c70b64..9f05cdcf 100644 --- a/src/main/scala/Testing.scala +++ b/src/main/scala/Testing.scala @@ -66,7 +66,7 @@ run-$kind-tests-fast: $$(addprefix $$(output_dir)/, $$(addsuffix .run, $targets) } else { "\n" } } - val f = createOutputFile("Makefrag-tests." + Driver.chiselConfigClassName.get) + val f = createOutputFile(s"${Driver.topComponent.name}.${Driver.chiselConfigClassName.get}.d") f.write(List(gen("asm", asmSuites.values.toSeq), gen("bmark", bmarkSuites.values.toSeq)).mkString("\n")) f.close } diff --git a/vsim/Makefile b/vsim/Makefile index 013d2f5b..84024df1 100644 --- a/vsim/Makefile +++ b/vsim/Makefile @@ -21,8 +21,8 @@ TB ?= rocketTestHarness include $(base_dir)/Makefrag include $(sim_dir)/Makefrag --include $(generated_dir)/Makefrag-tests.$(CONFIG) -include $(base_dir)/vsim/Makefrag-sim +-include $(generated_dir)/$(MODEL).$(CONFIG).d +include $(base_dir)/vsim/Makefrag-verilog all: $(simv) debug: $(simv_debug) diff --git a/vsim/Makefrag b/vsim/Makefrag index b3af766b..a1f91b11 100644 --- a/vsim/Makefrag +++ b/vsim/Makefrag @@ -50,13 +50,13 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1 # Build the simulator #-------------------------------------------------------------------- -simv = $(sim_dir)/simv-$(CONFIG) +simv = $(sim_dir)/simv-$(MODEL)-$(CONFIG) $(simv) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a cd $(sim_dir) && \ $(VCS) $(VCS_OPTS) -o $(simv) \ -debug_pp \ -simv_debug = $(sim_dir)/simv-$(CONFIG)-debug +simv_debug = $(sim_dir)/simv-$(MODEL)-$(CONFIG)-debug $(simv_debug) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a cd $(sim_dir) && \ $(VCS) $(VCS_OPTS) -o $(simv_debug) \ diff --git a/vsim/Makefrag-sim b/vsim/Makefrag-verilog similarity index 60% rename from vsim/Makefrag-sim rename to vsim/Makefrag-verilog index 826999f8..6a8d8302 100644 --- a/vsim/Makefrag-sim +++ b/vsim/Makefrag-verilog @@ -1,3 +1,23 @@ +#-------------------------------------------------------------------- +# Verilog Generation +#-------------------------------------------------------------------- + +$(generated_dir)/$(MODEL).$(CONFIG).v $(generated_dir)/$(MODEL).$(CONFIG).d : $(chisel_srcs) + cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "run $(CHISEL_ARGS) --configDump --noInlineMem" + cd $(generated_dir) && \ + if [ -a $(MODEL).$(CONFIG).conf ]; then \ + $(mem_gen) $(generated_dir)/$(MODEL).$(CONFIG).conf >> $(generated_dir)/$(MODEL).$(CONFIG).v; \ + fi + +$(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(MODEL).$(CONFIG).v + echo "\`ifndef CONST_VH" > $@ + echo "\`define CONST_VH" >> $@ + sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $(patsubst %.v,%.prm,$<) >> $@ + echo "\`endif // CONST_VH" >> $@ + +$(generated_dir)/memdessertMemDessert.$(CONFIG).v $(generated_dir)/memdessertMemDessert.$(CONFIG).d: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala + cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "run MemDessert --backend v --targetDir $(generated_dir) --W0W --moduleNamePrefix memdessert --configInstance rocketchip.$(CONFIG)" + #-------------------------------------------------------------------- # Run #--------------------------------------------------------------------