riscv/rocket-chip
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replace remaining uses of Vec.fill

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This commit is contained in:
Howard Mao 2015-09-24 17:50:09 -07:00
parent 3ff830e118
commit d1f2d40a90
1 changed files with 5 additions and 5 deletions
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10
uncore/src/main/scala/cache.scala
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@ -157,7 +157,7 @@ class MetadataArray[T <: Metadata](makeRstVal: () => T) extends CacheModule {
val metabits = rstVal.getWidth val metabits = rstVal.getWidth
val tag_arr = SeqMem(Vec(UInt(width = metabits), nWays), nSets) val tag_arr = SeqMem(Vec(UInt(width = metabits), nWays), nSets)
when (rst || io.write.valid) { when (rst || io.write.valid) {
tag_arr.write(waddr, Vec.fill(nWays)(wdata), wmask) tag_arr.write(waddr, Vec(nWays, wdata), wmask)
} }
val tags = tag_arr.read(io.read.bits.idx, io.read.valid).toBits val tags = tag_arr.read(io.read.bits.idx, io.read.valid).toBits
@ -493,7 +493,7 @@ class L2VoluntaryReleaseTracker(trackerId: Int) extends L2XactTracker {
val state = Reg(init=s_idle) val state = Reg(init=s_idle)
val xact = Reg(Bundle(new ReleaseFromSrc, { case TLId => params(InnerTLId); case TLDataBits => 0 })) val xact = Reg(Bundle(new ReleaseFromSrc, { case TLId => params(InnerTLId); case TLDataBits => 0 }))
val data_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits))) val data_buffer = Reg(init=Vec(innerDataBeats, UInt(0, innerDataBits)))
val xact_way_en = Reg{ Bits(width = nWays) } val xact_way_en = Reg{ Bits(width = nWays) }
val xact_old_meta = Reg{ new L2Metadata } val xact_old_meta = Reg{ new L2Metadata }
val coh = xact_old_meta.coh val coh = xact_old_meta.coh
@ -588,8 +588,8 @@ class L2AcquireTracker(trackerId: Int) extends L2XactTracker {
// State holding transaction metadata // State holding transaction metadata
val xact = Reg(Bundle(new AcquireFromSrc, { case TLId => params(InnerTLId) })) val xact = Reg(Bundle(new AcquireFromSrc, { case TLId => params(InnerTLId) }))
val data_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits))) val data_buffer = Reg(init=Vec(innerDataBeats, UInt(0, innerDataBits)))
val wmask_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits/8))) val wmask_buffer = Reg(init=Vec(innerDataBeats, UInt(0, innerDataBits/8)))
val xact_tag_match = Reg{ Bool() } val xact_tag_match = Reg{ Bool() }
val xact_way_en = Reg{ Bits(width = nWays) } val xact_way_en = Reg{ Bits(width = nWays) }
val xact_old_meta = Reg{ new L2Metadata } val xact_old_meta = Reg{ new L2Metadata }
@ -981,7 +981,7 @@ class L2WritebackUnit(trackerId: Int) extends L2XactTracker {
val state = Reg(init=s_idle) val state = Reg(init=s_idle)
val xact = Reg(new L2WritebackReq) val xact = Reg(new L2WritebackReq)
val data_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits))) val data_buffer = Reg(init=Vec(innerDataBeats, UInt(0, innerDataBits)))
val xact_addr_block = Cat(xact.tag, xact.idx) val xact_addr_block = Cat(xact.tag, xact.idx)
val pending_irels = val pending_irels =