From d1f2d40a908c45c31209c5eb3585cdd5bf8f7baa Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Thu, 24 Sep 2015 17:50:09 -0700 Subject: [PATCH] replace remaining uses of Vec.fill --- uncore/src/main/scala/cache.scala | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/uncore/src/main/scala/cache.scala b/uncore/src/main/scala/cache.scala index ff0d7739..6884165b 100644 --- a/uncore/src/main/scala/cache.scala +++ b/uncore/src/main/scala/cache.scala @@ -157,7 +157,7 @@ class MetadataArray[T <: Metadata](makeRstVal: () => T) extends CacheModule { val metabits = rstVal.getWidth val tag_arr = SeqMem(Vec(UInt(width = metabits), nWays), nSets) when (rst || io.write.valid) { - tag_arr.write(waddr, Vec.fill(nWays)(wdata), wmask) + tag_arr.write(waddr, Vec(nWays, wdata), wmask) } val tags = tag_arr.read(io.read.bits.idx, io.read.valid).toBits @@ -493,7 +493,7 @@ class L2VoluntaryReleaseTracker(trackerId: Int) extends L2XactTracker { val state = Reg(init=s_idle) val xact = Reg(Bundle(new ReleaseFromSrc, { case TLId => params(InnerTLId); case TLDataBits => 0 })) - val data_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits))) + val data_buffer = Reg(init=Vec(innerDataBeats, UInt(0, innerDataBits))) val xact_way_en = Reg{ Bits(width = nWays) } val xact_old_meta = Reg{ new L2Metadata } val coh = xact_old_meta.coh @@ -588,8 +588,8 @@ class L2AcquireTracker(trackerId: Int) extends L2XactTracker { // State holding transaction metadata val xact = Reg(Bundle(new AcquireFromSrc, { case TLId => params(InnerTLId) })) - val data_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits))) - val wmask_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits/8))) + val data_buffer = Reg(init=Vec(innerDataBeats, UInt(0, innerDataBits))) + val wmask_buffer = Reg(init=Vec(innerDataBeats, UInt(0, innerDataBits/8))) val xact_tag_match = Reg{ Bool() } val xact_way_en = Reg{ Bits(width = nWays) } val xact_old_meta = Reg{ new L2Metadata } @@ -981,7 +981,7 @@ class L2WritebackUnit(trackerId: Int) extends L2XactTracker { val state = Reg(init=s_idle) val xact = Reg(new L2WritebackReq) - val data_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits))) + val data_buffer = Reg(init=Vec(innerDataBeats, UInt(0, innerDataBits))) val xact_addr_block = Cat(xact.tag, xact.idx) val pending_irels =