rocketchip: remove most uses of GlobalAddrMap

riscv-tools

@@ -1 +1 @@
-Subproject commit 40919ef94f7e6426785bf534fb018ae8d0d79fb3
+Subproject commit 886d8131dbd23533fb04d2d76a80be21d5f9ee7a

src/main/scala/coreplex/BaseCoreplex.scala

@@ -45,7 +45,6 @@ trait HasCoreplexParameters {
   implicit val p: Parameters
   lazy val cbusConfig = p(CBusConfig)
   lazy val l1tol2Config = p(L1toL2Config)
-  lazy val globalAddrMap = p(rocketchip.GlobalAddrMap)
   lazy val nTiles = p(uncore.devices.NTiles)
   lazy val hasSupervisor = p(rocket.UseVM)
   lazy val l2Config = p(BankedL2Config)

src/main/scala/coreplex/Configs.scala

@@ -14,7 +14,6 @@ import uncore.converters._
 import rocket._
 import util._
 import util.ConfigUtils._
-import rocketchip.{GlobalAddrMap}
 import config._
 
 class BaseCoreplexConfig extends Config (

src/main/scala/groundtest/BusMasterTest.scala

@@ -5,7 +5,6 @@ import uncore.tilelink._
 import uncore.agents._
 import uncore.coherence.{InnerTLId, OuterTLId}
 import util._
-import junctions.HasAddrMapParameters
 import rocketchip._
 import config._
 
@@ -17,7 +16,6 @@ import config._
  * means it has finished.
  */
 class ExampleBusMaster(implicit val p: Parameters) extends Module
-    with HasAddrMapParameters
     with HasTileLinkParameters {
   val mmioParams = p.alterPartial({ case TLId => p(InnerTLId) })
   val memParams = p.alterPartial({ case TLId => p(OuterTLId) })

src/main/scala/groundtest/Regression.scala

@@ -5,7 +5,6 @@ import uncore.tilelink._
 import uncore.constants._
 import uncore.agents._
 import util._
-import junctions.HasAddrMapParameters
 import rocket._
 import rocketchip._
 import config._
@@ -19,7 +18,7 @@ class RegressionIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
 }
 
 abstract class Regression(implicit val p: Parameters)
-    extends Module with HasTileLinkParameters with HasAddrMapParameters {
+    extends Module with HasTileLinkParameters {
   val memStart = p(ExtMem).base
   val memStartBlock = memStart >> p(CacheBlockOffsetBits)
   val io = new RegressionIO

src/main/scala/groundtest/Tile.scala

@@ -9,7 +9,6 @@ import rocketchip.ExtMem
 import diplomacy._
 import scala.util.Random
 import scala.collection.mutable.ListBuffer
-import junctions.HasAddrMapParameters
 import util.ParameterizedBundle
 import config._
 

src/main/scala/groundtest/TraceGen.scala

@@ -178,7 +178,6 @@ class TagMan(val logNumTags : Int) extends Module {
 
 class TraceGenerator(id: Int)
     (implicit p: Parameters) extends L1HellaCacheModule()(p)
-                                with HasAddrMapParameters
                                 with HasTraceGenParams
                                 with HasGroundTestParameters {
   val io = new Bundle {

src/main/scala/rocketchip/Utils.scala

@@ -85,7 +85,6 @@ object GenerateGlobalAddrMap {
 object GenerateConfigString {
   def apply(p: Parameters, clint: CoreplexLocalInterrupter, plic: TLPLIC, peripheryManagers: Seq[TLManagerParameters]) = {
     val c = CoreplexParameters()(p)
-    val addrMap = p(GlobalAddrMap)
     val res = new StringBuilder
     res append plic.module.globalConfigString
     res append clint.module.globalConfigString

src/main/scala/uncore/converters/Ahb.scala

@@ -35,8 +35,7 @@ class AHBRequestIO(implicit p: Parameters) extends HastiMasterIO
 // AHB stage1: translate TileLink Acquires into AHBRequests
 class AHBTileLinkIn(supportAtomics: Boolean = false)(implicit val p: Parameters) extends Module
     with HasHastiParameters
-    with HasTileLinkParameters
-    with HasAddrMapParameters {
+    with HasTileLinkParameters {
   val io = new Bundle {
     val acquire = new DecoupledIO(new Acquire).flip // NOTE: acquire must be either a Queue or a Pipe
     val request = new DecoupledIO(new AHBRequestIO)
@@ -238,8 +237,7 @@ class AHBTileLinkIn(supportAtomics: Boolean = false)(implicit val p: Parameters)
 // AHB stage2: execute AHBRequests
 class AHBBusMaster(supportAtomics: Boolean = false)(implicit val p: Parameters) extends Module
     with HasHastiParameters
-    with HasTileLinkParameters
-    with HasAddrMapParameters {
+    with HasTileLinkParameters {
   val io = new Bundle {
     val request = new DecoupledIO(new AHBRequestIO).flip
     val grant   = new DecoupledIO(new Grant)
@@ -390,8 +388,7 @@ class AHBBusMaster(supportAtomics: Boolean = false)(implicit val p: Parameters)
 
 class AHBBridge(supportAtomics: Boolean = true)(implicit val p: Parameters) extends Module
     with HasHastiParameters
-    with HasTileLinkParameters
-    with HasAddrMapParameters {
+    with HasTileLinkParameters {
   val io = new Bundle {
     val tl  = new ClientUncachedTileLinkIO().flip
     val ahb = new HastiMasterIO()

src/main/scala/uncore/devices/Rom.scala

@@ -47,8 +47,7 @@ class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], exec
 }
 
 class ROMSlave(contents: Seq[Byte])(implicit val p: Parameters) extends Module
-    with HasTileLinkParameters
-    with HasAddrMapParameters {
+    with HasTileLinkParameters {
   val io = new ClientUncachedTileLinkIO().flip
 
   val acq = Queue(io.acquire, 1)