From d1328a6b6fde2e172e4d81f705d66f4b5daf953b Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 18 Nov 2016 19:38:02 -0800 Subject: [PATCH] rocketchip: remove most uses of GlobalAddrMap --- riscv-tools | 2 +- src/main/scala/coreplex/BaseCoreplex.scala | 1 - src/main/scala/coreplex/Configs.scala | 1 - src/main/scala/groundtest/BusMasterTest.scala | 2 -- src/main/scala/groundtest/Regression.scala | 3 +-- src/main/scala/groundtest/Tile.scala | 1 - src/main/scala/groundtest/TraceGen.scala | 1 - src/main/scala/rocketchip/Utils.scala | 1 - src/main/scala/uncore/converters/Ahb.scala | 9 +++------ src/main/scala/uncore/devices/Rom.scala | 3 +-- 10 files changed, 6 insertions(+), 18 deletions(-) diff --git a/riscv-tools b/riscv-tools index 40919ef9..886d8131 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit 40919ef94f7e6426785bf534fb018ae8d0d79fb3 +Subproject commit 886d8131dbd23533fb04d2d76a80be21d5f9ee7a diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala index 7123c50e..21255209 100644 --- a/src/main/scala/coreplex/BaseCoreplex.scala +++ b/src/main/scala/coreplex/BaseCoreplex.scala @@ -45,7 +45,6 @@ trait HasCoreplexParameters { implicit val p: Parameters lazy val cbusConfig = p(CBusConfig) lazy val l1tol2Config = p(L1toL2Config) - lazy val globalAddrMap = p(rocketchip.GlobalAddrMap) lazy val nTiles = p(uncore.devices.NTiles) lazy val hasSupervisor = p(rocket.UseVM) lazy val l2Config = p(BankedL2Config) diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala index 82746a89..13986aa0 100644 --- a/src/main/scala/coreplex/Configs.scala +++ b/src/main/scala/coreplex/Configs.scala @@ -14,7 +14,6 @@ import uncore.converters._ import rocket._ import util._ import util.ConfigUtils._ -import rocketchip.{GlobalAddrMap} import config._ class BaseCoreplexConfig extends Config ( diff --git a/src/main/scala/groundtest/BusMasterTest.scala b/src/main/scala/groundtest/BusMasterTest.scala index ad12c808..8a745fc7 100644 --- a/src/main/scala/groundtest/BusMasterTest.scala +++ b/src/main/scala/groundtest/BusMasterTest.scala @@ -5,7 +5,6 @@ import uncore.tilelink._ import uncore.agents._ import uncore.coherence.{InnerTLId, OuterTLId} import util._ -import junctions.HasAddrMapParameters import rocketchip._ import config._ @@ -17,7 +16,6 @@ import config._ * means it has finished. */ class ExampleBusMaster(implicit val p: Parameters) extends Module - with HasAddrMapParameters with HasTileLinkParameters { val mmioParams = p.alterPartial({ case TLId => p(InnerTLId) }) val memParams = p.alterPartial({ case TLId => p(OuterTLId) }) diff --git a/src/main/scala/groundtest/Regression.scala b/src/main/scala/groundtest/Regression.scala index eaee1dbe..6652c583 100644 --- a/src/main/scala/groundtest/Regression.scala +++ b/src/main/scala/groundtest/Regression.scala @@ -5,7 +5,6 @@ import uncore.tilelink._ import uncore.constants._ import uncore.agents._ import util._ -import junctions.HasAddrMapParameters import rocket._ import rocketchip._ import config._ @@ -19,7 +18,7 @@ class RegressionIO(implicit val p: Parameters) extends ParameterizedBundle()(p) } abstract class Regression(implicit val p: Parameters) - extends Module with HasTileLinkParameters with HasAddrMapParameters { + extends Module with HasTileLinkParameters { val memStart = p(ExtMem).base val memStartBlock = memStart >> p(CacheBlockOffsetBits) val io = new RegressionIO diff --git a/src/main/scala/groundtest/Tile.scala b/src/main/scala/groundtest/Tile.scala index d418ceba..d889bfb3 100644 --- a/src/main/scala/groundtest/Tile.scala +++ b/src/main/scala/groundtest/Tile.scala @@ -9,7 +9,6 @@ import rocketchip.ExtMem import diplomacy._ import scala.util.Random import scala.collection.mutable.ListBuffer -import junctions.HasAddrMapParameters import util.ParameterizedBundle import config._ diff --git a/src/main/scala/groundtest/TraceGen.scala b/src/main/scala/groundtest/TraceGen.scala index 3a514e3e..1280a7db 100644 --- a/src/main/scala/groundtest/TraceGen.scala +++ b/src/main/scala/groundtest/TraceGen.scala @@ -178,7 +178,6 @@ class TagMan(val logNumTags : Int) extends Module { class TraceGenerator(id: Int) (implicit p: Parameters) extends L1HellaCacheModule()(p) - with HasAddrMapParameters with HasTraceGenParams with HasGroundTestParameters { val io = new Bundle { diff --git a/src/main/scala/rocketchip/Utils.scala b/src/main/scala/rocketchip/Utils.scala index 329c352e..f0aaeb9d 100644 --- a/src/main/scala/rocketchip/Utils.scala +++ b/src/main/scala/rocketchip/Utils.scala @@ -85,7 +85,6 @@ object GenerateGlobalAddrMap { object GenerateConfigString { def apply(p: Parameters, clint: CoreplexLocalInterrupter, plic: TLPLIC, peripheryManagers: Seq[TLManagerParameters]) = { val c = CoreplexParameters()(p) - val addrMap = p(GlobalAddrMap) val res = new StringBuilder res append plic.module.globalConfigString res append clint.module.globalConfigString diff --git a/src/main/scala/uncore/converters/Ahb.scala b/src/main/scala/uncore/converters/Ahb.scala index d9457065..d6f236d2 100644 --- a/src/main/scala/uncore/converters/Ahb.scala +++ b/src/main/scala/uncore/converters/Ahb.scala @@ -35,8 +35,7 @@ class AHBRequestIO(implicit p: Parameters) extends HastiMasterIO // AHB stage1: translate TileLink Acquires into AHBRequests class AHBTileLinkIn(supportAtomics: Boolean = false)(implicit val p: Parameters) extends Module with HasHastiParameters - with HasTileLinkParameters - with HasAddrMapParameters { + with HasTileLinkParameters { val io = new Bundle { val acquire = new DecoupledIO(new Acquire).flip // NOTE: acquire must be either a Queue or a Pipe val request = new DecoupledIO(new AHBRequestIO) @@ -238,8 +237,7 @@ class AHBTileLinkIn(supportAtomics: Boolean = false)(implicit val p: Parameters) // AHB stage2: execute AHBRequests class AHBBusMaster(supportAtomics: Boolean = false)(implicit val p: Parameters) extends Module with HasHastiParameters - with HasTileLinkParameters - with HasAddrMapParameters { + with HasTileLinkParameters { val io = new Bundle { val request = new DecoupledIO(new AHBRequestIO).flip val grant = new DecoupledIO(new Grant) @@ -390,8 +388,7 @@ class AHBBusMaster(supportAtomics: Boolean = false)(implicit val p: Parameters) class AHBBridge(supportAtomics: Boolean = true)(implicit val p: Parameters) extends Module with HasHastiParameters - with HasTileLinkParameters - with HasAddrMapParameters { + with HasTileLinkParameters { val io = new Bundle { val tl = new ClientUncachedTileLinkIO().flip val ahb = new HastiMasterIO() diff --git a/src/main/scala/uncore/devices/Rom.scala b/src/main/scala/uncore/devices/Rom.scala index f46ce22e..3cfab1e4 100644 --- a/src/main/scala/uncore/devices/Rom.scala +++ b/src/main/scala/uncore/devices/Rom.scala @@ -47,8 +47,7 @@ class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], exec } class ROMSlave(contents: Seq[Byte])(implicit val p: Parameters) extends Module - with HasTileLinkParameters - with HasAddrMapParameters { + with HasTileLinkParameters { val io = new ClientUncachedTileLinkIO().flip val acq = Queue(io.acquire, 1)