riscv/rocket-chip
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rocketchip: remove most uses of GlobalAddrMap

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This commit is contained in:
Wesley W. Terpstra
2016-11-18 19:38:02 -08:00
parent 2976fd84e4
commit d1328a6b6f
10 changed files with 6 additions and 18 deletions
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9
src/main/scala/uncore/converters/Ahb.scala
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@ -35,8 +35,7 @@ class AHBRequestIO(implicit p: Parameters) extends HastiMasterIO
// AHB stage1: translate TileLink Acquires into AHBRequests
class AHBTileLinkIn(supportAtomics: Boolean = false)(implicit val p: Parameters) extends Module
with HasHastiParameters
with HasTileLinkParameters
with HasAddrMapParameters {
with HasTileLinkParameters {
val io = new Bundle {
val acquire = new DecoupledIO(new Acquire).flip // NOTE: acquire must be either a Queue or a Pipe
val request = new DecoupledIO(new AHBRequestIO)
@ -238,8 +237,7 @@ class AHBTileLinkIn(supportAtomics: Boolean = false)(implicit val p: Parameters)
// AHB stage2: execute AHBRequests
class AHBBusMaster(supportAtomics: Boolean = false)(implicit val p: Parameters) extends Module
with HasHastiParameters
with HasTileLinkParameters
with HasAddrMapParameters {
with HasTileLinkParameters {
val io = new Bundle {
val request = new DecoupledIO(new AHBRequestIO).flip
val grant = new DecoupledIO(new Grant)
@ -390,8 +388,7 @@ class AHBBusMaster(supportAtomics: Boolean = false)(implicit val p: Parameters)
class AHBBridge(supportAtomics: Boolean = true)(implicit val p: Parameters) extends Module
with HasHastiParameters
with HasTileLinkParameters
with HasAddrMapParameters {
with HasTileLinkParameters {
val io = new Bundle {
val tl = new ClientUncachedTileLinkIO().flip
val ahb = new HastiMasterIO()

3
src/main/scala/uncore/devices/Rom.scala
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@ -47,8 +47,7 @@ class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], exec
}
class ROMSlave(contents: Seq[Byte])(implicit val p: Parameters) extends Module
with HasTileLinkParameters
with HasAddrMapParameters {
with HasTileLinkParameters {
val io = new ClientUncachedTileLinkIO().flip
val acq = Queue(io.acquire, 1)