rocketchip: remove most uses of GlobalAddrMap

src/main/scala/groundtest/BusMasterTest.scala

@@ -5,7 +5,6 @@ import uncore.tilelink._
 import uncore.agents._
 import uncore.coherence.{InnerTLId, OuterTLId}
 import util._
-import junctions.HasAddrMapParameters
 import rocketchip._
 import config._
 
@@ -17,7 +16,6 @@ import config._
  * means it has finished.
  */
 class ExampleBusMaster(implicit val p: Parameters) extends Module
-    with HasAddrMapParameters
     with HasTileLinkParameters {
   val mmioParams = p.alterPartial({ case TLId => p(InnerTLId) })
   val memParams = p.alterPartial({ case TLId => p(OuterTLId) })

src/main/scala/groundtest/Regression.scala

@@ -5,7 +5,6 @@ import uncore.tilelink._
 import uncore.constants._
 import uncore.agents._
 import util._
-import junctions.HasAddrMapParameters
 import rocket._
 import rocketchip._
 import config._
@@ -19,7 +18,7 @@ class RegressionIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
 }
 
 abstract class Regression(implicit val p: Parameters)
-    extends Module with HasTileLinkParameters with HasAddrMapParameters {
+    extends Module with HasTileLinkParameters {
   val memStart = p(ExtMem).base
   val memStartBlock = memStart >> p(CacheBlockOffsetBits)
   val io = new RegressionIO

src/main/scala/groundtest/Tile.scala

@@ -9,7 +9,6 @@ import rocketchip.ExtMem
 import diplomacy._
 import scala.util.Random
 import scala.collection.mutable.ListBuffer
-import junctions.HasAddrMapParameters
 import util.ParameterizedBundle
 import config._
 

src/main/scala/groundtest/TraceGen.scala

@@ -178,7 +178,6 @@ class TagMan(val logNumTags : Int) extends Module {
 
 class TraceGenerator(id: Int)
     (implicit p: Parameters) extends L1HellaCacheModule()(p)
-                                with HasAddrMapParameters
                                 with HasTraceGenParams
                                 with HasGroundTestParameters {
   val io = new Bundle {