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axi4 Bundles: add a size calculation helper

The old version was wrong.
Inverting before the << has a different width.
This means you end up with high bits set.
This commit is contained in:
Wesley W. Terpstra 2016-10-16 21:59:39 -07:00
parent ee66fd28eb
commit d09f43c32f
2 changed files with 8 additions and 1 deletions

View File

@ -20,6 +20,13 @@ abstract class AXI4BundleA(params: AXI4BundleParameters) extends AXI4BundleBase(
val prot = UInt(width = params.protBits)
val qos = UInt(width = params.qosBits) // 0=no QoS, bigger = higher priority
// val region = UInt(width = 4) // optional
// Number of bytes-1 in this operation
def bytes1(x:Int=0) = {
val maxShift = 1 << params.sizeBits
val tail = UInt((BigInt(1) << maxShift) - 1)
(Cat(len, tail) << size) >> maxShift
}
}
// A non-standard bundle that can be both AR and AW

View File

@ -103,7 +103,7 @@ class AXI4Fragmenter(lite: Boolean = false, maxInFlight: Int = 32, combinational
val beats = ~(~(beats1 << 1 | UInt(1)) | beats1) // beats1 + 1
val inc_addr = addr + (beats << a.bits.size) // address after adding transfer
val wrapMask = ~(~a.bits.len << a.bits.size) // only these bits may change, if wrapping
val wrapMask = a.bits.bytes1() // only these bits may change, if wrapping
val mux_addr = Wire(init = inc_addr)
when (a.bits.burst === AXI4Parameters.BURST_WRAP) {
mux_addr := (inc_addr & wrapMask) | ~(~a.bits.addr | wrapMask)