diff --git a/src/main/scala/uncore/axi4/Bundles.scala b/src/main/scala/uncore/axi4/Bundles.scala
index 89fdbc9f..95068cab 100644
--- a/src/main/scala/uncore/axi4/Bundles.scala
+++ b/src/main/scala/uncore/axi4/Bundles.scala
@@ -20,6 +20,13 @@ abstract class AXI4BundleA(params: AXI4BundleParameters) extends AXI4BundleBase(
   val prot   = UInt(width = params.protBits)
   val qos    = UInt(width = params.qosBits)  // 0=no QoS, bigger = higher priority
   // val region = UInt(width = 4) // optional
+
+  // Number of bytes-1 in this operation
+  def bytes1(x:Int=0) = {
+    val maxShift = 1 << params.sizeBits
+    val tail = UInt((BigInt(1) << maxShift) - 1)
+    (Cat(len, tail) << size) >> maxShift
+  }
 }
 
 // A non-standard bundle that can be both AR and AW
diff --git a/src/main/scala/uncore/axi4/Fragmenter.scala b/src/main/scala/uncore/axi4/Fragmenter.scala
index 57015359..3fd714f7 100644
--- a/src/main/scala/uncore/axi4/Fragmenter.scala
+++ b/src/main/scala/uncore/axi4/Fragmenter.scala
@@ -103,7 +103,7 @@ class AXI4Fragmenter(lite: Boolean = false, maxInFlight: Int = 32, combinational
       val beats = ~(~(beats1 << 1 | UInt(1)) | beats1) // beats1 + 1
 
       val inc_addr = addr + (beats << a.bits.size) // address after adding transfer
-      val wrapMask = ~(~a.bits.len << a.bits.size) // only these bits may change, if wrapping
+      val wrapMask = a.bits.bytes1() // only these bits may change, if wrapping
       val mux_addr = Wire(init = inc_addr)
       when (a.bits.burst === AXI4Parameters.BURST_WRAP) {
         mux_addr := (inc_addr & wrapMask) | ~(~a.bits.addr | wrapMask)