riscv/rocket-chip
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zero: fix attachment in multichannel case (#870)

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Wesley W. Terpstra 2017-07-17 21:48:31 -07:00 committed by GitHub
parent fc75ada577
commit d09a985729
2 changed files with 12 additions and 9 deletions
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15
src/main/scala/chip/Periphery.scala
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@ -143,8 +143,8 @@ trait HasPeripheryMasterAXI4MemPort extends HasSystemNetworks {
resources = device.reg, resources = device.reg,
regionType = RegionType.UNCACHED, // cacheable regionType = RegionType.UNCACHED, // cacheable
executable = true, executable = true,
supportsWrite = TransferSizes(1, 256), // The slave supports 1-256 byte transfers supportsWrite = TransferSizes(1, blockBytes),
supportsRead = TransferSizes(1, 256), supportsRead = TransferSizes(1, blockBytes),
interleavedId = Some(0))), // slave does not interleave read responses interleavedId = Some(0))), // slave does not interleave read responses
beatBytes = config.beatBytes) beatBytes = config.beatBytes)
}) })
@ -334,11 +334,16 @@ trait HasPeripherySlaveTLPortModuleImp extends LazyMultiIOModuleImp with HasPeri
/** Adds a /dev/null slave that generates */ /** Adds a /dev/null slave that generates */
trait HasPeripheryZeroSlave extends HasSystemNetworks { trait HasPeripheryZeroSlave extends HasSystemNetworks {
private val config = p(ZeroConfig) private val config = p(ZeroConfig)
private val address = AddressSet(config.base, config.size-1) private val channels = p(BankedL2Config).nMemoryChannels
private val blockBytes = p(CacheBlockBytes) private val blockBytes = p(CacheBlockBytes)
val zeros = mem map { case xbar => private val device = new SimpleDevice("rom", Seq("ucbbar,cacheable-zero0"))
val zero = LazyModule(new TLZero(address, beatBytes = config.beatBytes))
val zeros = mem.zipWithIndex.map { case (xbar, channel) =>
val base = AddressSet(config.base, config.size-1)
val filter = AddressSet(channel * blockBytes, ~((channels-1) * blockBytes))
val address = base.intersect(filter).get
val zero = LazyModule(new TLZero(address, beatBytes = config.beatBytes, resources = device.reg("mem")))
zero.node := TLFragmenter(config.beatBytes, blockBytes)(xbar.node) zero.node := TLFragmenter(config.beatBytes, blockBytes)(xbar.node)
zero zero
} }

6
src/main/scala/devices/tilelink/Zero.scala
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@ -7,14 +7,12 @@ import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._ import freechips.rocketchip.tilelink._
class TLZero(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule class TLZero(address: AddressSet, resources: Seq[Resource], executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
{ {
val device = new SimpleDevice("rom", Seq("ucbbar,cacheable-zero0"))
val node = TLManagerNode(Seq(TLManagerPortParameters( val node = TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters( Seq(TLManagerParameters(
address = List(address), address = List(address),
resources = device.reg("mem"), resources = resources,
regionType = RegionType.UNCACHED, regionType = RegionType.UNCACHED,
executable = executable, executable = executable,
supportsGet = TransferSizes(1, beatBytes), supportsGet = TransferSizes(1, beatBytes),