diff --git a/src/main/scala/chip/Periphery.scala b/src/main/scala/chip/Periphery.scala
index 933af820..26d30d9c 100644
--- a/src/main/scala/chip/Periphery.scala
+++ b/src/main/scala/chip/Periphery.scala
@@ -143,8 +143,8 @@ trait HasPeripheryMasterAXI4MemPort extends HasSystemNetworks {
         resources     = device.reg,
         regionType    = RegionType.UNCACHED,   // cacheable
         executable    = true,
-        supportsWrite = TransferSizes(1, 256), // The slave supports 1-256 byte transfers
-        supportsRead  = TransferSizes(1, 256),
+        supportsWrite = TransferSizes(1, blockBytes),
+        supportsRead  = TransferSizes(1, blockBytes),
         interleavedId = Some(0))),             // slave does not interleave read responses
       beatBytes = config.beatBytes)
   })
@@ -334,11 +334,16 @@ trait HasPeripherySlaveTLPortModuleImp extends LazyMultiIOModuleImp with HasPeri
 /** Adds a /dev/null slave that generates */
 trait HasPeripheryZeroSlave extends HasSystemNetworks {
   private val config = p(ZeroConfig)
-  private val address = AddressSet(config.base, config.size-1)
+  private val channels = p(BankedL2Config).nMemoryChannels
   private val blockBytes = p(CacheBlockBytes)
 
-  val zeros = mem map { case xbar =>
-    val zero = LazyModule(new TLZero(address, beatBytes = config.beatBytes))
+  private val device = new SimpleDevice("rom", Seq("ucbbar,cacheable-zero0"))
+
+  val zeros = mem.zipWithIndex.map { case (xbar, channel) =>
+    val base = AddressSet(config.base, config.size-1)
+    val filter = AddressSet(channel * blockBytes, ~((channels-1) * blockBytes))
+    val address = base.intersect(filter).get
+    val zero = LazyModule(new TLZero(address, beatBytes = config.beatBytes, resources = device.reg("mem")))
     zero.node := TLFragmenter(config.beatBytes, blockBytes)(xbar.node)
     zero
   }
diff --git a/src/main/scala/devices/tilelink/Zero.scala b/src/main/scala/devices/tilelink/Zero.scala
index 9463d9cb..51bb0782 100644
--- a/src/main/scala/devices/tilelink/Zero.scala
+++ b/src/main/scala/devices/tilelink/Zero.scala
@@ -7,14 +7,12 @@ import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 
-class TLZero(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
+class TLZero(address: AddressSet, resources: Seq[Resource], executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
 {
-  val device = new SimpleDevice("rom", Seq("ucbbar,cacheable-zero0"))
-
   val node = TLManagerNode(Seq(TLManagerPortParameters(
     Seq(TLManagerParameters(
       address            = List(address),
-      resources          = device.reg("mem"),
+      resources          = resources,
       regionType         = RegionType.UNCACHED,
       executable         = executable,
       supportsGet        = TransferSizes(1, beatBytes),