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coreplex: WithStatelessBridge => WithIncoherentTiles (#1092)

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Henry Cook 2017-11-07 13:47:56 -08:00 committed by GitHub
parent bdda2cb145
commit d096fd206b
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2 changed files with 7 additions and 8 deletions
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12
src/main/scala/coreplex/Configs.scala
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@ -151,13 +151,13 @@ class WithBufferlessBroadcastHub extends Config((site, here, up) => {
* system depends on coherence between channels in any way, * system depends on coherence between channels in any way,
* DO NOT use this configuration. * DO NOT use this configuration.
*/ */
class WithStatelessBridge extends Config((site, here, up) => { class WithIncoherentTiles extends Config((site, here, up) => {
case RocketCrossingKey => up(RocketCrossingKey, site) map { r =>
r.copy(master = r.master.copy(cork = Some(true)))
}
case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = { coreplex => case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = { coreplex =>
implicit val p = coreplex.p val ww = LazyModule(new TLWidthWidget(coreplex.sbusBeatBytes)(coreplex.p))
val ww = LazyModule(new TLWidthWidget(coreplex.sbusBeatBytes)) (ww.node, ww.node, () => None)
val cc = LazyModule(new TLCacheCork(unsafe = true))
cc.node :*= ww.node
(ww.node, cc.node, () => None)
}) })
}) })

3
src/main/scala/system/Configs.scala
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@ -65,11 +65,10 @@ class DualCoreConfig extends Config(
class TinyConfig extends Config( class TinyConfig extends Config(
new WithNMemoryChannels(0) ++ new WithNMemoryChannels(0) ++
new WithStatelessBridge ++ new WithIncoherentTiles ++
new With1TinyCore ++ new With1TinyCore ++
new BaseConfig) new BaseConfig)
class BaseFPGAConfig extends Config(new BaseConfig) class BaseFPGAConfig extends Config(new BaseConfig)
class DefaultFPGAConfig extends Config(new WithNSmallCores(1) ++ new BaseFPGAConfig) class DefaultFPGAConfig extends Config(new WithNSmallCores(1) ++ new BaseFPGAConfig)