riscv/rocket-chip
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new enum syntax

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This commit is contained in:
Henry Cook
2013-09-10 10:51:35 -07:00
parent cfbfa6b895
commit d06e24ac24
6 changed files with 9 additions and 9 deletions
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rocket/src/main/scala/ptw.scala
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@ -39,7 +39,7 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module
val bitsPerLevel = VPN_BITS/levels
require(VPN_BITS == levels * bitsPerLevel)
val s_ready :: s_req :: s_wait :: s_done :: s_error :: Nil = Enum(5) { UInt() };
val s_ready :: s_req :: s_wait :: s_done :: s_error :: Nil = Enum(UInt(), 5)
val state = Reg(init=s_ready)
val count = Reg(UInt(width = log2Up(levels)))