From d06e24ac243d6b519cba88cb66e15cb63792914c Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 10 Sep 2013 10:51:35 -0700 Subject: [PATCH] new enum syntax --- rocket/src/main/scala/divider.scala | 4 ++-- rocket/src/main/scala/htif.scala | 4 ++-- rocket/src/main/scala/icache.scala | 2 +- rocket/src/main/scala/nbdcache.scala | 4 ++-- rocket/src/main/scala/ptw.scala | 2 +- rocket/src/main/scala/tlb.scala | 2 +- 6 files changed, 9 insertions(+), 9 deletions(-) diff --git a/rocket/src/main/scala/divider.scala b/rocket/src/main/scala/divider.scala index bfdfcb2e..c18e47d6 100644 --- a/rocket/src/main/scala/divider.scala +++ b/rocket/src/main/scala/divider.scala @@ -9,7 +9,7 @@ class MulDiv(mulUnroll: Int = 1, earlyOut: Boolean = false)(implicit conf: Rocke val w = io.req.bits.in1.getWidth val mulw = (w+mulUnroll-1)/mulUnroll*mulUnroll - val s_ready :: s_neg_inputs :: s_mul_busy :: s_div_busy :: s_move_rem :: s_neg_output :: s_done :: Nil = Enum(7) { UInt() }; + val s_ready :: s_neg_inputs :: s_mul_busy :: s_div_busy :: s_move_rem :: s_neg_output :: s_done :: Nil = Enum(UInt(), 7) val state = Reg(init=s_ready) val req = Reg(io.req.bits.clone) @@ -122,7 +122,7 @@ class Divider(earlyOut: Boolean = false)(implicit conf: RocketConfiguration) ext val io = new MultiplierIO val w = io.req.bits.in1.getWidth - val s_ready :: s_neg_inputs :: s_busy :: s_move_rem :: s_neg_output :: s_done :: Nil = Enum(6) { UInt() }; + val s_ready :: s_neg_inputs :: s_busy :: s_move_rem :: s_neg_output :: s_done :: Nil = Enum(UInt(), 6) val state = Reg(init=s_ready) val count = Reg(UInt(width = log2Up(w+1))) diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala index 6df4d28c..2392f3c6 100644 --- a/rocket/src/main/scala/htif.scala +++ b/rocket/src/main/scala/htif.scala @@ -89,7 +89,7 @@ class RocketHTIF(w: Int, nSCR: Int)(implicit conf: TileLinkConfiguration) extend packet_ram(rx_word_count(log2Up(packet_ram_depth)-1,0) - UInt(1)) := rx_shifter_in } - val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(6) { UInt() } + val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(UInt(), 6) val pcr_addr = addr(io.cpu(0).pcr_req.bits.addr.width-1, 0) val pcr_coreid = addr(log2Up(nTiles)-1+20+1,20) @@ -124,7 +124,7 @@ class RocketHTIF(w: Int, nSCR: Int)(implicit conf: TileLinkConfiguration) extend } io.mem.grant.ready := Bool(true) - val state_rx :: state_pcr_req :: state_pcr_resp :: state_mem_req :: state_mem_wdata :: state_mem_wresp :: state_mem_rdata :: state_mem_finish :: state_tx :: Nil = Enum(9) { UInt() } + val state_rx :: state_pcr_req :: state_pcr_resp :: state_mem_req :: state_mem_wdata :: state_mem_wresp :: state_mem_rdata :: state_mem_finish :: state_tx :: Nil = Enum(UInt(), 9) val state = Reg(init=state_rx) val rx_cmd = Mux(rx_word_count === UInt(0), next_cmd, cmd) diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index bae95113..17c6e88b 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -143,7 +143,7 @@ class ICache(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Module val mem = new UncachedTileLinkIO } - val s_ready :: s_request :: s_refill_wait :: s_refill :: Nil = Enum(4) { UInt() } + val s_ready :: s_request :: s_refill_wait :: s_refill :: Nil = Enum(UInt(), 4) val state = Reg(init=s_ready) val invalidated = Reg(Bool()) val stall = !io.resp.ready diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index 5e8b4c96..89c772a4 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -188,7 +188,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig, tl: TileLinkConfiguration) exte val probe_rdy = Bool(OUTPUT) } - val s_invalid :: s_wb_req :: s_wb_resp :: s_meta_clear :: s_refill_req :: s_refill_resp :: s_meta_write_req :: s_meta_write_resp :: s_drain_rpq :: Nil = Enum(9) { UInt() } + val s_invalid :: s_wb_req :: s_wb_resp :: s_meta_clear :: s_refill_req :: s_refill_resp :: s_meta_write_req :: s_meta_write_resp :: s_drain_rpq :: Nil = Enum(UInt(), 9) val state = Reg(init=s_invalid) val acquire_type = Reg(UInt()) @@ -505,7 +505,7 @@ class ProbeUnit(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends val line_state = UInt(INPUT, 2) } - val s_reset :: s_invalid :: s_meta_read :: s_meta_resp :: s_mshr_req :: s_release :: s_writeback_req :: s_writeback_resp :: s_meta_write :: Nil = Enum(9) { UInt() } + val s_reset :: s_invalid :: s_meta_read :: s_meta_resp :: s_mshr_req :: s_release :: s_writeback_req :: s_writeback_resp :: s_meta_write :: Nil = Enum(UInt(), 9) val state = Reg(init=s_invalid) val line_state = Reg(UInt()) val way_en = Reg(Bits()) diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala index f4acb1c5..af5787e6 100644 --- a/rocket/src/main/scala/ptw.scala +++ b/rocket/src/main/scala/ptw.scala @@ -39,7 +39,7 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module val bitsPerLevel = VPN_BITS/levels require(VPN_BITS == levels * bitsPerLevel) - val s_ready :: s_req :: s_wait :: s_done :: s_error :: Nil = Enum(5) { UInt() }; + val s_ready :: s_req :: s_wait :: s_done :: s_error :: Nil = Enum(UInt(), 5) val state = Reg(init=s_ready) val count = Reg(UInt(width = log2Up(levels))) diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala index 0e9d6112..45d5078a 100644 --- a/rocket/src/main/scala/tlb.scala +++ b/rocket/src/main/scala/tlb.scala @@ -93,7 +93,7 @@ class TLB(entries: Int) extends Module val ptw = new TLBPTWIO } - val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(4) { UInt() } + val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(UInt(), 4) val state = Reg(init=s_ready) val r_refill_tag = Reg(UInt()) val r_refill_waddr = Reg(UInt())