riscv/rocket-chip
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This commit is contained in:
Andrew Waterman
2014-03-04 16:38:34 -08:00
parent 23045ec379
commit d055c0ebaf
6 changed files with 8 additions and 9 deletions
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2
chisel

Submodule chisel updated: 56e8b23ff2...25a33ba1d4

2
csrc/emulator.cc
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@@ -125,7 +125,7 @@ int main(int argc, char** argv)
} }
if (log) if (log)
tile.print(stderr, stderr); tile.print(stderr);
if (vcd) if (vcd)
tile.dump(vcdfile, trace_count); tile.dump(vcdfile, trace_count);

2
hardfloat

Submodule hardfloat updated: d126925915...39a08130d4

2
rocket

Submodule rocket updated: f08e60a165...49f633cd12

4
src/main/scala/RocketChip.scala
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@@ -256,8 +256,8 @@ class Top extends Module {
nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates) nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)
val vic = ICacheConfig(128, 1) val vic = ICacheConfig(128, 1)
val hc = hwacha.HwachaConfiguration(vic, dc, 8, 256, ndtlb = 8, nptlb = 2) val hc = hwacha.HwachaConfiguration(vic, dc, 8, 256, ndtlb = 8, nptlb = 2)
val rc = RocketConfiguration(tl, ic, dc, val fpu = if (HAS_FPU) Some(FPUConfig(sfmaLatency = 2, dfmaLatency = 3)) else None
fpu = HAS_FPU val rc = RocketConfiguration(tl, ic, dc, fpu
//,rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c)) //,rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c))
) )

5
src/main/scala/fpga.scala
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@@ -92,9 +92,8 @@ class FPGATop extends Module {
val ic = ICacheConfig(64, 1, ntlb = 4, nbtb = 4) val ic = ICacheConfig(64, 1, ntlb = 4, nbtb = 4)
val dc = DCacheConfig(64, 1, ntlb = 4, nmshr = 2, nrpq = 16, nsdq = 17, states = co.nClientStates) val dc = DCacheConfig(64, 1, ntlb = 4, nmshr = 2, nrpq = 16, nsdq = 17, states = co.nClientStates)
val rc = RocketConfiguration(tl, ic, dc, val rc = RocketConfiguration(tl, ic, dc, fpu = None,
fastMulDiv = false, fastMulDiv = false)
fpu = false)
val io = new FPGATopIO(htif_width) val io = new FPGATopIO(htif_width)