riscv/rocket-chip
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Andrew Waterman
2014-03-04 16:38:34 -08:00
parent 23045ec379
commit d055c0ebaf
6 changed files with 8 additions and 9 deletions
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4
src/main/scala/RocketChip.scala
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@ -256,8 +256,8 @@ class Top extends Module {
nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)
val vic = ICacheConfig(128, 1)
val hc = hwacha.HwachaConfiguration(vic, dc, 8, 256, ndtlb = 8, nptlb = 2)
val rc = RocketConfiguration(tl, ic, dc,
fpu = HAS_FPU
val fpu = if (HAS_FPU) Some(FPUConfig(sfmaLatency = 2, dfmaLatency = 3)) else None
val rc = RocketConfiguration(tl, ic, dc, fpu
//,rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c))
)

5
src/main/scala/fpga.scala
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@ -92,9 +92,8 @@ class FPGATop extends Module {
val ic = ICacheConfig(64, 1, ntlb = 4, nbtb = 4)
val dc = DCacheConfig(64, 1, ntlb = 4, nmshr = 2, nrpq = 16, nsdq = 17, states = co.nClientStates)
val rc = RocketConfiguration(tl, ic, dc,
fastMulDiv = false,
fpu = false)
val rc = RocketConfiguration(tl, ic, dc, fpu = None,
fastMulDiv = false)
val io = new FPGATopIO(htif_width)