riscv/rocket-chip
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Remove Hwacha from Rocket

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Soon it will use the coprocessor interface.
This commit is contained in:
Andrew Waterman
2013-09-12 22:34:38 -07:00
parent 1edb1e2a0a
commit d053bdc89f
10 changed files with 121 additions and 873 deletions
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109
rocket/src/main/scala/core.scala
View File

@@ -1,16 +1,15 @@
package rocket
import Chisel._
import hwacha._
import uncore.constants.MemoryOpConstants._
import Util._
class RocketIO(implicit conf: RocketConfiguration) extends Bundle
{
val host = new HTIFIO(conf.tl.ln.nClients)
val imem = new CPUFrontendIO()(conf.icache)
val vimem = new CPUFrontendIO()(conf.icache)
val dmem = new HellaCacheIO()(conf.dcache)
val host = new HTIFIO(conf.tl.ln.nClients)
val imem = new CPUFrontendIO()(conf.icache)
val dmem = new HellaCacheIO()(conf.dcache)
val ptw = new DatapathPTWIO().flip
}
class Core(implicit conf: RocketConfiguration) extends Module
@@ -26,107 +25,17 @@ class Core(implicit conf: RocketConfiguration) extends Module
ctrl.io.imem <> io.imem
dpath.io.imem <> io.imem
val dmemArb = Module(new HellaCacheArbiter(2 + conf.vec))
dmemArb.io.mem <> io.dmem
val dmem = dmemArb.io.requestor
dmem(1) <> ctrl.io.dmem
dmem(1) <> dpath.io.dmem
ctrl.io.dmem <> io.dmem
dpath.io.dmem <> io.dmem
val ptw = collection.mutable.ArrayBuffer(io.imem.ptw, io.dmem.ptw)
dpath.io.ptw <> io.ptw
val fpu: FPU = if (conf.fpu) {
val fpu = Module(new FPU(4,6))
dpath.io.fpu <> fpu.io.dpath
ctrl.io.fpu <> fpu.io.ctrl
fpu.io.sfma.valid := Bool(false) // hook these up to coprocessor?
fpu.io.dfma.valid := Bool(false)
fpu
} else null
if (conf.vec) {
val vu = Module(new vu(Reg(next=this.reset)))
val vdtlb = Module(new TLB(8))
ptw += vdtlb.io.ptw
vdtlb.io <> vu.io.vtlb
val pftlb = Module(new TLB(2))
pftlb.io <> vu.io.vpftlb
ptw += pftlb.io.ptw
dpath.io.vec_ctrl <> ctrl.io.vec_dpath
// hooking up vector I$
ptw += io.vimem.ptw
io.vimem.req.bits.pc := vu.io.imem_req.bits
io.vimem.req.valid := vu.io.imem_req.valid
io.vimem.invalidate := ctrl.io.imem.invalidate
vu.io.imem_resp.valid := io.vimem.resp.valid
vu.io.imem_resp.bits.pc := io.vimem.resp.bits.pc
vu.io.imem_resp.bits.data := io.vimem.resp.bits.data
vu.io.imem_resp.bits.xcpt_ma := io.vimem.resp.bits.xcpt_ma
vu.io.imem_resp.bits.xcpt_if := io.vimem.resp.bits.xcpt_if
io.vimem.resp.ready := vu.io.imem_resp.ready
io.vimem.req.bits.mispredict := Bool(false)
io.vimem.req.bits.taken := Bool(false)
ctrl.io.vec_iface.vcmdq <> vu.io.vcmdq
ctrl.io.vec_iface.vximm1q <> vu.io.vximm1q
ctrl.io.vec_iface.vximm2q <> vu.io.vximm2q
ctrl.io.vec_iface.vcntq <> vu.io.vcntq
dpath.io.vec_iface.vcmdq <> vu.io.vcmdq
dpath.io.vec_iface.vximm1q <> vu.io.vximm1q
dpath.io.vec_iface.vximm2q <> vu.io.vximm2q
dpath.io.vec_iface.vcntq <> vu.io.vcntq
ctrl.io.vec_iface.vpfcmdq <> vu.io.vpfcmdq
ctrl.io.vec_iface.vpfximm1q <> vu.io.vpfximm1q
ctrl.io.vec_iface.vpfximm2q <> vu.io.vpfximm2q
ctrl.io.vec_iface.vpfcntq <> vu.io.vpfcntq
dpath.io.vec_iface.vpfcmdq <> vu.io.vpfcmdq
dpath.io.vec_iface.vpfximm1q <> vu.io.vpfximm1q
dpath.io.vec_iface.vpfximm2q <> vu.io.vpfximm2q
dpath.io.vec_iface.vpfcntq <> vu.io.vpfcntq
// user level vector command queue ready signals
ctrl.io.vec_iface.vcmdq_user_ready := vu.io.vcmdq_user_ready
ctrl.io.vec_iface.vximm1q_user_ready := vu.io.vximm1q_user_ready
ctrl.io.vec_iface.vximm2q_user_ready := vu.io.vximm2q_user_ready
// fences
ctrl.io.vec_iface.vfence_ready := vu.io.vfence_ready
// irqs
ctrl.io.vec_iface.irq := vu.io.irq
ctrl.io.vec_iface.irq_cause := vu.io.irq_cause
dpath.io.vec_iface.irq_aux := vu.io.irq_aux
// exceptions
vu.io.xcpt.exception := ctrl.io.vec_iface.exception
vu.io.xcpt.evac := ctrl.io.vec_iface.evac
vu.io.xcpt.evac_addr := dpath.io.vec_iface.evac_addr.toUInt
vu.io.xcpt.kill := ctrl.io.vec_iface.kill
vu.io.xcpt.hold := ctrl.io.vec_iface.hold
// hooking up vector memory interface
dmem(2).req.bits.data := RegEnable(StoreGen(vu.io.dmem_req.bits).data, vu.io.dmem_req.valid && isWrite(vu.io.dmem_req.bits.cmd))
dmem(2).req <> vu.io.dmem_req
dmem(2).resp <> vu.io.dmem_resp
// DON'T share vector integer multiplier with rocket
vu.io.cp_imul_req.valid := Bool(false)
// share sfma and dfma pipelines with rocket
require(conf.fpu)
fpu.io.sfma <> vu.io.cp_sfma
fpu.io.dfma <> vu.io.cp_dfma
} else if (conf.fpu) {
fpu.io.sfma.valid := Bool(false)
fpu.io.dfma.valid := Bool(false)
}
val thePTW = Module(new PTW(ptw.length))
ptw zip thePTW.io.requestor map { case (a, b) => a <> b }
thePTW.io.dpath <> dpath.io.ptw
dmem(0) <> thePTW.io.mem
}

163
rocket/src/main/scala/ctrl.scala
View File

@@ -2,7 +2,6 @@ package rocket
import Chisel._
import Instructions._
import hwacha._
import uncore.constants.MemoryOpConstants._
import ALU._
import Util._
@@ -45,7 +44,6 @@ class CtrlDpathIO extends Bundle()
val exception = Bool(OUTPUT);
val cause = UInt(OUTPUT, 6);
val badvaddr_wen = Bool(OUTPUT); // high for a load/store access fault
val vec_irq_aux_wen = Bool(OUTPUT)
// inputs from datapath
val inst = Bits(INPUT, 32);
val jalr_eq = Bool(INPUT)
@@ -71,7 +69,7 @@ abstract trait DecodeConstants
// fence.i
// jalr mul_val | eret
// fp_val | renx2 | div_val | | syscall
// | vec_val | | renx1 s_alu1 mem_val | | wen pcr | | | privileged
// | rocc_val | | renx1 s_alu1 mem_val | | wen pcr | | | privileged
// val | | brtype | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | s_wb | | | | | replay_next
// | | | | | | | | | | | | | | | | | | | | | | | | | fence
// | | | | | | | | | | | | | | | | | | | | | | | | | | amo
@@ -87,7 +85,7 @@ object XDecode extends DecodeConstants
// fence.i
// jalr mul_val | eret
// fp_val | renx2 | div_val | | syscall
// | vec_val | | renx1 s_alu1 mem_val | | wen pcr | | | privileged
// | rocc_val | | renx1 s_alu1 mem_val | | wen pcr | | | privileged
// val | | brtype | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | s_wb | | | | | replay_next
// | | | | | | | | | | | | | | | | | | | | | | | | | fence
// | | | | | | | | | | | | | | | | | | | | | | | | | | amo
@@ -204,7 +202,7 @@ object FDecode extends DecodeConstants
// fence.i
// jalr mul_val | eret
// fp_val | renx2 | div_val | | syscall
// | vec_val | | renx1 s_alu1 mem_val | | wen pcr | | | privileged
// | rocc_val | | renx1 s_alu1 mem_val | | wen pcr | | | privileged
// val | | brtype | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | s_wb | | | | | replay_next
// | | | | | | | | | | | | | | | | | | | | | | | | | fence
// | | | | | | | | | | | | | | | | | | | | | | | | | | amo
@@ -269,61 +267,41 @@ object FDecode extends DecodeConstants
FSD-> List(Y, Y,N,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N))
}
object VDecode extends DecodeConstants
object RoCCDecode extends DecodeConstants
{
val table = Array(
// fence.i
// jalr mul_val | eret
// fp_val | renx2 | div_val | | syscall
// | vec_val | | renx1 s_alu1 mem_val | | wen pcr | | | privileged
// val | | brtype | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | s_wb | | | | | replay_next
// | | | | | | | | | | | | | | | | | | | | | | | | | fence
// | | | | | | | | | | | | | | | | | | | | | | | | | | amo
// | | | | | | | | | | | | | | | | | | | | | | | | | | |
VSETCFGVL-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,Y,N,N),
VSETVL-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,Y,N,N),
VF-> List(Y, N,Y,BR_N, N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VMVV-> List(Y, N,Y,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N),
FENCE_V_L-> List(Y, N,Y,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N),
FENCE_V_G-> List(Y, N,Y,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, Y,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,N,N,N,N),
VLD-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VLW-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VLWU-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VLH-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VLHU-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VLB-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VLBU-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VSD-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VSW-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VSH-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VSB-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VFLD-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VFLW-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VFSD-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VFSW-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VLSTD-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VLSTW-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VLSTWU-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VLSTH-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VLSTHU-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VLSTB-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VLSTBU-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VSSTD-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VSSTW-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VSSTH-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VSSTB-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VFLSTD-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VFLSTW-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VFSSTD-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VFSSTW-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_D, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
VENQCMD-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,Y,N,N,N),
VENQIMM1-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,Y,N,N,N),
VENQIMM2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,Y,N,N,N),
VENQCNT-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,Y,N,N,N),
VXCPTEVAC-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,Y,N,N,N),
VXCPTKILL-> List(Y, N,Y,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,Y,N,N,N),
VXCPTHOLD-> List(Y, N,Y,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,WB_X, PCR.N,N,N,N,Y,N,N,N))
// fence.i
// jalr mul_val | eret
// fp_val | renx2 | div_val | | syscall
// | rocc_val | | renx1 s_alu1 mem_val | | wen pcr | | | privileged
// val | | brtype | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | s_wb | | | | | replay_next
// | | | | | | | | | | | | | | | | | | | | | | | | | fence
// | | | | | | | | | | | | | | | | | | | | | | | | | | amo
// | | | | | | | | | | | | | | | | | | | | | | | | | | |
CUSTOM0-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
CUSTOM0_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
CUSTOM0_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
CUSTOM0-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N),
CUSTOM0_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N),
CUSTOM0_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N),
CUSTOM1-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
CUSTOM1_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
CUSTOM1_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
CUSTOM1-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N),
CUSTOM1_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N),
CUSTOM1_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N),
CUSTOM2-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
CUSTOM2_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
CUSTOM2_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
CUSTOM2-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N),
CUSTOM2_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N),
CUSTOM2_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N),
CUSTOM3-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
CUSTOM3_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
CUSTOM3_RS1_RS2-> List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,WB_ALU,PCR.N,N,N,N,N,N,N,N),
CUSTOM3-> List(Y, N,Y,BR_N, N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N),
CUSTOM3_RD_RS1-> List(Y, N,Y,BR_N, N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N),
CUSTOM3_RD_RS1_RS2->List(Y, N,Y,BR_N, N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WB_ALU,PCR.N,N,N,N,N,N,N,N))
}
class Control(implicit conf: RocketConfiguration) extends Module
@@ -339,13 +317,11 @@ class Control(implicit conf: RocketConfiguration) extends Module
val xcpt_dtlb_ld = Bool(INPUT)
val xcpt_dtlb_st = Bool(INPUT)
val fpu = new CtrlFPUIO
val vec_dpath = new CtrlDpathVecIO
val vec_iface = new CtrlVecInterfaceIO
}
var decode_table = XDecode.table
if (conf.fpu) decode_table ++= FDecode.table
if (conf.vec) decode_table ++= VDecode.table
if (!conf.rocc.isEmpty) decode_table ++= RoCCDecode.table
val logic = DecodeLogic(io.dpath.inst, XDecode.decode_default, decode_table)
val cs = logic.map {
@@ -353,7 +329,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
case u => u
}
val (id_int_val: Bool) :: (id_fp_val: Bool) :: (id_vec_val: Bool) :: id_br_type :: (id_jalr: Bool) :: (id_renx2: Bool) :: (id_renx1: Bool) :: cs0 = cs
val (id_int_val: Bool) :: (id_fp_val: Bool) :: (id_rocc_val: Bool) :: id_br_type :: (id_jalr: Bool) :: (id_renx2: Bool) :: (id_renx1: Bool) :: cs0 = cs
val id_sel_alu2 :: id_sel_alu1 :: id_sel_imm :: (id_fn_dw: Bool) :: id_fn_alu :: cs1 = cs0
val (id_mem_val: Bool) :: id_mem_cmd :: id_mem_type :: (id_mul_val: Bool) :: (id_div_val: Bool) :: (id_wen: Bool) :: id_sel_wb :: cs2 = cs1
val id_pcr :: (id_fence_i: Bool) :: (id_eret: Bool) :: (id_syscall: Bool) :: (id_privileged: Bool) :: (id_replay_next: Bool) :: (id_fence: Bool) :: (id_amo: Bool) :: Nil = cs2
@@ -370,7 +346,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
val ex_reg_mem_val = Reg(init=Bool(false))
val ex_reg_xcpt = Reg(init=Bool(false))
val ex_reg_fp_val = Reg(init=Bool(false))
val ex_reg_vec_val = Reg(init=Bool(false))
val ex_reg_rocc_val = Reg(init=Bool(false))
val ex_reg_replay_next = Reg(init=Bool(false))
val ex_reg_load_use = Reg(init=Bool(false))
val ex_reg_pcr = Reg(init=PCR.N)
@@ -389,7 +365,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
val mem_reg_mem_val = Reg(init=Bool(false))
val mem_reg_xcpt = Reg(init=Bool(false))
val mem_reg_fp_val = Reg(init=Bool(false))
val mem_reg_vec_val = Reg(init=Bool(false))
val mem_reg_rocc_val = Reg(init=Bool(false))
val mem_reg_replay = Reg(init=Bool(false))
val mem_reg_replay_next = Reg(init=Bool(false))
val mem_reg_pcr = Reg(init=PCR.N)
@@ -426,43 +402,6 @@ class Control(implicit conf: RocketConfiguration) extends Module
val sr = io.dpath.status
var id_interrupts = (0 until sr.ip.getWidth).map(i => (sr.im(i) && sr.ip(i), UInt(CAUSE_INTERRUPT+i)))
val (vec_replay, vec_stalld) = if (conf.vec) {
// vector control
val vec = Module(new rocketCtrlVec)
io.vec_dpath <> vec.io.dpath
io.vec_iface <> vec.io.iface
vec.io.valid := wb_reg_valid
vec.io.s := io.dpath.status.s
vec.io.sr_ev := io.dpath.status.ev
vec.io.exception := wb_reg_xcpt
vec.io.eret := wb_reg_eret
val vec_dec = Module(new rocketCtrlVecDecoder)
vec_dec.io.inst := io.dpath.inst
val s = io.dpath.status.s
val mask_cmdq_ready = !vec_dec.io.sigs.enq_cmdq || s && io.vec_iface.vcmdq.ready || !s && io.vec_iface.vcmdq_user_ready
val mask_ximm1q_ready = !vec_dec.io.sigs.enq_ximm1q || s && io.vec_iface.vximm1q.ready || !s && io.vec_iface.vximm1q_user_ready
val mask_ximm2q_ready = !vec_dec.io.sigs.enq_ximm2q || s && io.vec_iface.vximm2q.ready || !s && io.vec_iface.vximm2q_user_ready
val mask_cntq_ready = !vec_dec.io.sigs.enq_cntq || io.vec_iface.vcntq.ready
val mask_pfcmdq_ready = !vec_dec.io.sigs.enq_pfcmdq || io.vec_iface.vpfcmdq.ready
val mask_pfximm1q_ready = !vec_dec.io.sigs.enq_pfximm1q || io.vec_iface.vpfximm1q.ready
val mask_pfximm2q_ready = !vec_dec.io.sigs.enq_pfximm2q || io.vec_iface.vpfximm2q.ready
val mask_pfcntq_ready = !vec_dec.io.sigs.enq_pfcntq || io.vec_iface.vpfcntq.ready
id_interrupts = id_interrupts :+ (vec.io.irq, vec.io.irq_cause)
val stalld =
id_vec_val && (
!mask_cmdq_ready || !mask_ximm1q_ready || !mask_ximm2q_ready || !mask_cntq_ready ||
!mask_pfcmdq_ready || !mask_pfximm1q_ready || !mask_pfximm2q_ready || !mask_pfcntq_ready ||
vec_dec.io.sigs.vfence && !vec.io.vfence_ready)
(vec.io.replay, stalld)
} else (Bool(false), Bool(false))
val (id_interrupt_unmasked, id_interrupt_cause) = checkExceptions(id_interrupts)
val id_interrupt = io.dpath.status.ei && id_interrupt_unmasked
@@ -489,7 +428,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
(id_privileged && !io.dpath.status.s, UInt(3)),
(id_fp_val && !io.dpath.status.ef, UInt(4)),
(id_syscall, UInt(6)),
(id_vec_val && !io.dpath.status.ev, UInt(12))))
(id_rocc_val && !io.dpath.status.er, UInt(12))))
ex_reg_xcpt_interrupt := id_interrupt && !take_pc && io.imem.resp.valid
when (id_xcpt) { ex_reg_cause := id_cause }
@@ -505,7 +444,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
ex_reg_eret := Bool(false);
ex_reg_flush_inst := Bool(false);
ex_reg_fp_val := Bool(false)
ex_reg_vec_val := Bool(false)
ex_reg_rocc_val := Bool(false)
ex_reg_replay_next := Bool(false)
ex_reg_load_use := Bool(false)
ex_reg_pcr := PCR.N
@@ -525,7 +464,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
ex_reg_eret := id_eret.toBool;
ex_reg_flush_inst := id_fence_i
ex_reg_fp_val := id_fp_val
ex_reg_vec_val := id_vec_val.toBool
ex_reg_rocc_val := id_rocc_val.toBool
ex_reg_replay_next := id_replay_next || id_pcr_flush
ex_reg_load_use := id_load_use
ex_reg_mem_cmd := id_mem_cmd
@@ -564,7 +503,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
mem_reg_mem_val := Bool(false);
mem_reg_flush_inst := Bool(false);
mem_reg_fp_val := Bool(false)
mem_reg_vec_val := Bool(false)
mem_reg_rocc_val := Bool(false)
mem_reg_replay_next := Bool(false)
mem_reg_xcpt := Bool(false)
}
@@ -577,7 +516,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
mem_reg_mem_val := ex_reg_mem_val;
mem_reg_flush_inst := ex_reg_flush_inst;
mem_reg_fp_val := ex_reg_fp_val
mem_reg_vec_val := ex_reg_vec_val
mem_reg_rocc_val := ex_reg_rocc_val
mem_reg_replay_next := ex_reg_replay_next
mem_reg_slow_bypass := ex_slow_bypass
mem_reg_xcpt := ex_xcpt
@@ -591,7 +530,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
(mem_reg_mem_val && io.dmem.xcpt.pf.st, UInt(11))))
val fpu_kill_mem = mem_reg_fp_val && io.fpu.nack_mem
val ll_wb_kill_mem = io.dpath.mem_ll_wb && (mem_reg_wen || mem_reg_fp_wen || mem_reg_vec_val || mem_reg_pcr != PCR.N)
val ll_wb_kill_mem = io.dpath.mem_ll_wb && (mem_reg_wen || mem_reg_fp_wen || mem_reg_rocc_val || mem_reg_pcr != PCR.N)
val replay_mem = ll_wb_kill_mem || mem_reg_replay || fpu_kill_mem
val killm_common = ll_wb_kill_mem || take_pc_wb || mem_reg_xcpt || !mem_reg_valid
ctrl_killm := killm_common || mem_xcpt || fpu_kill_mem
@@ -623,7 +562,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
wb_reg_fp_val := mem_reg_fp_val
}
val replay_wb = io.dmem.resp.bits.nack || wb_reg_replay || vec_replay || io.dpath.pcr_replay
val replay_wb = io.dmem.resp.bits.nack || wb_reg_replay || io.dpath.pcr_replay
class Scoreboard(n: Int)
{
@@ -667,7 +606,6 @@ class Control(implicit conf: RocketConfiguration) extends Module
io.dpath.exception := wb_reg_xcpt
io.dpath.cause := wb_reg_cause
io.dpath.badvaddr_wen := wb_reg_xcpt && (wb_reg_cause === UInt(10) || wb_reg_cause === UInt(11))
io.dpath.vec_irq_aux_wen := wb_reg_xcpt && wb_reg_cause >= UInt(24) && wb_reg_cause < UInt(32)
// control transfer from ex/wb
take_pc_wb := replay_wb || wb_reg_xcpt || wb_reg_eret
@@ -737,8 +675,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
id_ex_hazard || id_mem_hazard || id_wb_hazard || id_sboard_hazard ||
id_fp_val && id_stall_fpu ||
id_mem_val && !io.dmem.req.ready ||
id_do_fence && !id_fence_ok ||
vec_stalld
id_do_fence && !id_fence_ok
val ctrl_draind = id_interrupt || ex_reg_replay_next
ctrl_killd := !io.imem.resp.valid || take_pc || ctrl_stalld || ctrl_draind
@@ -770,8 +707,8 @@ class Control(implicit conf: RocketConfiguration) extends Module
io.dpath.eret := wb_reg_eret
io.dpath.ex_mem_type := ex_reg_mem_type
io.dpath.ex_br_type := ex_reg_br_type
io.dpath.ex_rs2_val := ex_reg_mem_val && isWrite(ex_reg_mem_cmd) || ex_reg_vec_val
io.dpath.mem_rs2_val := mem_reg_vec_val
io.dpath.ex_rs2_val := ex_reg_mem_val && isWrite(ex_reg_mem_cmd) || ex_reg_rocc_val
io.dpath.mem_rs2_val := mem_reg_rocc_val
io.fpu.valid := !ctrl_killd && id_fp_val
io.fpu.killx := ctrl_killx

273
rocket/src/main/scala/ctrl_vec.scala
View File

@@ -1,273 +0,0 @@
package rocket
import Chisel._
import Instructions._
import hwacha.Constants._
class CtrlDpathVecIO extends Bundle
{
val inst = Bits(INPUT, 32)
val appvl0 = Bool(INPUT)
val pfq = Bool(INPUT)
val wen = Bool(OUTPUT)
val fn = Bits(OUTPUT, 2)
val sel_vcmd = Bits(OUTPUT, 3)
val sel_vimm = Bits(OUTPUT, 1)
val sel_vimm2 = Bits(OUTPUT, 1)
}
class CtrlVecInterfaceIO extends Bundle
{
val vcmdq = Decoupled(Bits(width = SZ_VCMD))
val vximm1q = Decoupled(Bits(width = SZ_VIMM))
val vximm2q = Decoupled(Bits(width = SZ_VSTRIDE))
val vcntq = Decoupled(Bits(width = SZ_VLEN+1))
val vpfcmdq = Decoupled(Bits(width = SZ_VCMD))
val vpfximm1q = Decoupled(Bits(width = SZ_VIMM))
val vpfximm2q = Decoupled(Bits(width = SZ_VSTRIDE))
val vpfcntq = Decoupled(Bits(width = SZ_VLEN))
val vcmdq_user_ready = Bool(INPUT)
val vximm1q_user_ready = Bool(INPUT)
val vximm2q_user_ready = Bool(INPUT)
val vfence_ready = Bool(INPUT)
val irq = Bool(INPUT)
val irq_cause = UInt(INPUT, 5)
val exception = Bool(OUTPUT)
val evac = Bool(OUTPUT)
val kill = Bool(OUTPUT)
val hold = Bool(OUTPUT)
}
class CtrlVecIO extends Bundle
{
val dpath = new CtrlDpathVecIO
val iface = new CtrlVecInterfaceIO
val valid = Bool(INPUT)
val s = Bool(INPUT)
val sr_ev = Bool(INPUT)
val exception = Bool(INPUT)
val eret = Bool(INPUT)
val replay = Bool(OUTPUT)
val vfence_ready = Bool(OUTPUT)
val irq = Bool(OUTPUT)
val irq_cause = UInt(OUTPUT, 5)
}
class rocketCtrlVecSigs extends Bundle
{
val valid = Bool()
val sel_vcmd = Bits(width = 3)
val sel_vimm = Bits(width = 1)
val sel_vimm2 = Bits(width = 1)
val wen = Bool()
val fn = Bits(width = 2)
val appvlmask = Bool()
val enq_cmdq = Bool()
val enq_ximm1q = Bool()
val enq_ximm2q = Bool()
val enq_cntq = Bool()
val enq_pfcmdq = Bool()
val enq_pfximm1q = Bool()
val enq_pfximm2q = Bool()
val enq_pfcntq = Bool()
val pfaq = Bool()
val vfence = Bool()
val xcptevac = Bool()
val xcptkill = Bool()
val xcpthold = Bool()
}
class rocketCtrlVecDecoder extends Module
{
val io = new Bundle
{
val inst = Bits(INPUT, 32)
val sigs = new rocketCtrlVecSigs().asOutput
}
val veccs =
ListLookup(io.inst,
// appvlmask
// | vcmdq
// | | vximm1q
// | | | vximm2q
// | | | | vcntq
// | | | | | vpfcmdq
// | | | | | | vpfximm1q
// | | | | | | | vpfximm2q
// | | | | | | | | vpfcntq
// | | | | | | | | | pfq
// | | | | | | | | | | vfence
// | | | | | | | | | | | xcptevac
// | | | | | | | | | | | | xcptkill
// wen | | | | | | | | | | | | | xcpthold
// val vcmd vimm vimm2 | fn | | | | | | | | | | | | | |
// | | | | | | | | | | | | | | | | | | | |
List(N,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,N,N,N,N),Array(
VSETCFGVL-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, Y,VEC_CFGVL,N,Y,Y,N,N,Y,Y,N,N,N,Y,N,N,N),
VSETVL-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, Y,VEC_VL, N,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VF-> List(Y,VCMD_I, VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,N,N,N,N,N,N,N,N,N),
VMVV-> List(Y,VCMD_TX,VIMM_X, VIMM2_X, N,VEC_FN_N, Y,Y,N,N,N,N,N,N,N,N,N,N,N,N),
FENCE_V_L-> List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,Y,N,N,N),
FENCE_V_G-> List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,Y,N,N,N),
VLD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VLW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VLWU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VLH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VLHU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VLB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VLBU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VSD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VSW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VSH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VSB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VFLD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VFLW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VFSD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VFSW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
VLSTD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VLSTW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VLSTWU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VLSTH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VLSTHU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VLSTB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VLSTBU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VSSTD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VSSTW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VSSTH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VSSTB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VFLSTD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VFLSTW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VFSSTD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VFSSTW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
VENQCMD-> List(Y,VCMD_A, VIMM_X, VIMM2_X, N,VEC_FN_N, N,Y,N,N,N,Y,N,N,N,Y,N,N,N,N),
VENQIMM1-> List(Y,VCMD_X, VIMM_ALU, VIMM2_X, N,VEC_FN_N, N,N,Y,N,N,N,Y,N,N,Y,N,N,N,N),
VENQIMM2-> List(Y,VCMD_X, VIMM_X, VIMM2_ALU,N,VEC_FN_N, N,N,N,Y,N,N,N,Y,N,Y,N,N,N,N),
VENQCNT-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,Y,N,N,N,Y,Y,N,N,N,N),
VXCPTEVAC-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,N,Y,N,N),
VXCPTKILL-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,N,N,Y,N),
VXCPTHOLD-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,N,N,N,Y)
))
val valid :: sel_vcmd :: sel_vimm :: sel_vimm2 :: wen :: fn :: appvlmask :: veccs0 = veccs
val enq_cmdq :: enq_ximm1q :: enq_ximm2q :: enq_cntq :: veccs1 = veccs0
val enq_pfcmdq :: enq_pfximm1q :: enq_pfximm2q :: enq_pfcntq :: veccs2 = veccs1
val pfaq :: vfence :: xcptevac :: xcptkill :: xcpthold :: Nil = veccs2
io.sigs.valid := valid.toBool
io.sigs.sel_vcmd := sel_vcmd
io.sigs.sel_vimm := sel_vimm
io.sigs.sel_vimm2 := sel_vimm2
io.sigs.wen := wen.toBool
io.sigs.fn := fn
io.sigs.appvlmask := appvlmask.toBool
io.sigs.enq_cmdq := enq_cmdq.toBool
io.sigs.enq_ximm1q := enq_ximm1q.toBool
io.sigs.enq_ximm2q := enq_ximm2q.toBool
io.sigs.enq_cntq := enq_cntq.toBool
io.sigs.enq_pfcmdq := enq_pfcmdq.toBool
io.sigs.enq_pfximm1q := enq_pfximm1q.toBool
io.sigs.enq_pfximm2q := enq_pfximm2q.toBool
io.sigs.enq_pfcntq := enq_pfcntq.toBool
io.sigs.pfaq := pfaq.toBool
io.sigs.vfence := vfence.toBool
io.sigs.xcptevac := xcptevac.toBool
io.sigs.xcptkill := xcptkill.toBool
io.sigs.xcpthold := xcpthold.toBool
}
class rocketCtrlVec extends Module
{
val io = new CtrlVecIO
val dec = Module(new rocketCtrlVecDecoder)
dec.io.inst := io.dpath.inst
val valid_common = io.valid && io.sr_ev && dec.io.sigs.valid && !(dec.io.sigs.appvlmask && io.dpath.appvl0)
val enq_pfcmdq_mask_pfq = dec.io.sigs.enq_pfcmdq && (!dec.io.sigs.pfaq || io.dpath.pfq)
val enq_pfximm1q_mask_pfq = dec.io.sigs.enq_pfximm1q && (!dec.io.sigs.pfaq || io.dpath.pfq)
val enq_pfximm2q_mask_pfq = dec.io.sigs.enq_pfximm2q && (!dec.io.sigs.pfaq || io.dpath.pfq)
val enq_pfcntq_mask_pfq = dec.io.sigs.enq_pfcntq && (!dec.io.sigs.pfaq || io.dpath.pfq)
val mask_cmdq_ready = !dec.io.sigs.enq_cmdq || io.s && io.iface.vcmdq.ready || !io.s && io.iface.vcmdq_user_ready
val mask_ximm1q_ready = !dec.io.sigs.enq_ximm1q || io.s && io.iface.vximm1q.ready || !io.s && io.iface.vximm1q_user_ready
val mask_ximm2q_ready = !dec.io.sigs.enq_ximm2q || io.s && io.iface.vximm2q.ready || !io.s && io.iface.vximm2q_user_ready
val mask_cntq_ready = !dec.io.sigs.enq_cntq || io.iface.vcntq.ready
val mask_pfcmdq_ready = !enq_pfcmdq_mask_pfq || io.iface.vpfcmdq.ready
val mask_pfximm1q_ready = !enq_pfximm1q_mask_pfq || io.iface.vpfximm1q.ready
val mask_pfximm2q_ready = !enq_pfximm2q_mask_pfq || io.iface.vpfximm2q.ready
val mask_pfcntq_ready = !enq_pfcntq_mask_pfq || io.iface.vpfcntq.ready
io.dpath.wen := dec.io.sigs.wen
io.dpath.fn := dec.io.sigs.fn
io.dpath.sel_vcmd := dec.io.sigs.sel_vcmd
io.dpath.sel_vimm := dec.io.sigs.sel_vimm
io.dpath.sel_vimm2 := dec.io.sigs.sel_vimm2
io.iface.vcmdq.valid :=
valid_common &&
dec.io.sigs.enq_cmdq && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready &&
mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready
io.iface.vximm1q.valid :=
valid_common &&
mask_cmdq_ready && dec.io.sigs.enq_ximm1q && mask_ximm2q_ready && mask_cntq_ready &&
mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready
io.iface.vximm2q.valid :=
valid_common &&
mask_cmdq_ready && mask_ximm1q_ready && dec.io.sigs.enq_ximm2q && mask_cntq_ready &&
mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready
io.iface.vcntq.valid :=
valid_common &&
mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && dec.io.sigs.enq_cntq &&
mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready
io.iface.vpfcmdq.valid :=
valid_common &&
mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready &&
enq_pfcmdq_mask_pfq && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready
io.iface.vpfximm1q.valid :=
valid_common &&
mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready &&
mask_pfcmdq_ready && enq_pfximm1q_mask_pfq && mask_pfximm2q_ready && mask_pfcntq_ready
io.iface.vpfximm2q.valid :=
valid_common &&
mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready &&
mask_pfcmdq_ready && mask_pfximm1q_ready && enq_pfximm2q_mask_pfq && mask_pfcntq_ready
io.iface.vpfcntq.valid :=
valid_common &&
mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready &&
mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && enq_pfcntq_mask_pfq
io.replay := valid_common && (
!mask_cmdq_ready || !mask_ximm1q_ready || !mask_ximm2q_ready || !mask_cntq_ready ||
!mask_pfcmdq_ready || !mask_pfximm1q_ready || !mask_pfximm2q_ready || !mask_pfcntq_ready ||
dec.io.sigs.vfence && !io.iface.vfence_ready
)
io.iface.exception := io.exception && io.sr_ev
val reg_hold = Reg(init=Bool(false))
when (valid_common && dec.io.sigs.xcpthold) { reg_hold := Bool(true) }
when (io.eret) { reg_hold := Bool(false) }
io.iface.evac := valid_common && dec.io.sigs.xcptevac
io.iface.kill := valid_common && dec.io.sigs.xcptkill
io.iface.hold := reg_hold
io.vfence_ready := !io.sr_ev || io.iface.vfence_ready
io.irq := io.iface.irq
io.irq_cause := io.iface.irq_cause
}

26
rocket/src/main/scala/dpath.scala
View File

@@ -3,7 +3,6 @@ package rocket
import Chisel._
import Instructions._
import Util._
import hwacha._
import uncore.constants.AddressConstants._
class Datapath(implicit conf: RocketConfiguration) extends Module
@@ -15,8 +14,6 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
val ptw = (new DatapathPTWIO).flip
val imem = new CPUFrontendIO()(conf.icache)
val fpu = new DpathFPUIO
val vec_ctrl = (new CtrlDpathVecIO).flip
val vec_iface = new DpathVecInterfaceIO
}
// execute definitions
@@ -292,29 +289,6 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
Mux(io.ctrl.pcr != PCR.N, pcr.io.rw.rdata,
wb_reg_wdata))
if (conf.vec)
{
// vector datapath
val vec = Module(new rocketDpathVec)
vec.io.ctrl <> io.vec_ctrl
io.vec_iface <> vec.io.iface
vec.io.valid := io.ctrl.wb_valid && pcr.io.status.ev
vec.io.inst := wb_reg_inst
vec.io.vecbank := pcr.io.vecbank
vec.io.vecbankcnt := pcr.io.vecbankcnt
vec.io.wdata := wb_reg_wdata
vec.io.rs2 := wb_reg_store_data
pcr.io.vec_irq_aux := vec.io.irq_aux
pcr.io.vec_appvl := vec.io.appvl
pcr.io.vec_nxregs := vec.io.nxregs
pcr.io.vec_nfregs := vec.io.nfregs
when (vec.io.wen) { wb_wdata := vec.io.appvl }
}
when (wb_wen) { writeRF(wb_reg_waddr, wb_wdata) }
io.ctrl.wb_waddr := wb_reg_waddr

45
rocket/src/main/scala/dpath_util.scala
View File

@@ -60,7 +60,7 @@ class Status extends Bundle {
val ip = Bits(width = 8)
val im = Bits(width = 8)
val zero = Bits(width = 7)
val ev = Bool()
val er = Bool()
val vm = Bool()
val s64 = Bool()
val u64 = Bool()
@@ -99,8 +99,6 @@ object PCR
val FATC = 13
val SEND_IPI = 14
val CLR_IPI = 15
val VECBANK = 18
val VECCFG = 19
val STATS = 28
val RESET = 29
val TOHOST = 30
@@ -127,8 +125,6 @@ class PCR(implicit conf: RocketConfiguration) extends Module
val exception = Bool(INPUT)
val cause = UInt(INPUT, 6)
val badvaddr_wen = Bool(INPUT)
val vec_irq_aux = Bits(INPUT, conf.xprlen)
val vec_irq_aux_wen = Bool(INPUT)
val pc = UInt(INPUT, VADDR_BITS+1)
val eret = Bool(INPUT)
val ei = Bool(INPUT)
@@ -137,12 +133,7 @@ class PCR(implicit conf: RocketConfiguration) extends Module
val irq_timer = Bool(OUTPUT)
val irq_ipi = Bool(OUTPUT)
val replay = Bool(OUTPUT)
val vecbank = Bits(OUTPUT, 8)
val vecbankcnt = UInt(OUTPUT, 4)
val stats = Bool(OUTPUT)
val vec_appvl = UInt(INPUT, 12)
val vec_nxregs = UInt(INPUT, 6)
val vec_nfregs = UInt(INPUT, 6)
}
import PCR._
@@ -157,7 +148,6 @@ class PCR(implicit conf: RocketConfiguration) extends Module
val reg_sup0 = Reg(Bits(width = conf.xprlen))
val reg_sup1 = Reg(Bits(width = conf.xprlen))
val reg_ptbr = Reg(UInt(width = PADDR_BITS))
val reg_vecbank = Reg(init=SInt(-1,8).toBits)
val reg_stats = Reg(init=Bool(false))
val reg_status = Reg(new Status) // reset down below
@@ -193,17 +183,10 @@ class PCR(implicit conf: RocketConfiguration) extends Module
io.fatc := wen && addr === FATC
io.evec := Mux(io.exception, reg_evec.toSInt, reg_epc).toUInt
io.ptbr := reg_ptbr
io.vecbank := reg_vecbank
var cnt = UInt(0,4)
for (i <- 0 until 8)
cnt = cnt + reg_vecbank(i)
io.vecbankcnt := cnt(3,0)
io.stats := reg_stats
when (io.badvaddr_wen || io.vec_irq_aux_wen) {
val wdata = Mux(io.badvaddr_wen, io.rw.wdata, io.vec_irq_aux)
when (io.badvaddr_wen) {
val wdata = io.rw.wdata
val (upper, lower) = Split(wdata, VADDR_BITS)
val sign = Mux(lower.toSInt < SInt(0), upper.andR, upper.orR)
reg_badvaddr := Cat(sign, lower).toSInt
@@ -237,17 +220,16 @@ class PCR(implicit conf: RocketConfiguration) extends Module
val read_impl = Bits(2)
val read_ptbr = reg_ptbr(PADDR_BITS-1,PGIDX_BITS) << PGIDX_BITS
val read_veccfg = if (conf.vec) Cat(io.vec_nfregs, io.vec_nxregs, io.vec_appvl) else Bits(0)
val read_cause = reg_cause(reg_cause.getWidth-1) << conf.xprlen-1 | reg_cause(reg_cause.getWidth-2,0)
io.rw.rdata := AVec[Bits](
reg_sup0, reg_sup1, reg_epc, reg_badvaddr,
reg_ptbr, Bits(0)/*asid*/, reg_count, reg_compare,
reg_evec, reg_cause, io.status.toBits, io.host.id,
read_impl, read_impl/*x*/, read_impl/*x*/, read_impl/*x*/,
reg_vecbank/*x*/, read_veccfg/*x*/, reg_vecbank, read_veccfg,
reg_vecbank/*x*/, read_veccfg/*x*/, reg_vecbank/*x*/, read_veccfg/*x*/,
reg_vecbank/*x*/, read_veccfg/*x*/, reg_tohost/*x*/, reg_fromhost/*x*/,
reg_stats/*x*/, read_veccfg/*x*/, reg_tohost, reg_fromhost
reg_sup0, reg_sup1, reg_epc, reg_badvaddr,
reg_ptbr, Bits(0)/*asid*/, reg_count, reg_compare,
reg_evec, reg_cause, io.status.toBits, io.host.id,
read_impl, read_impl/*x*/, read_impl/*x*/, read_impl/*x*/,
reg_stats/*x*/, reg_fromhost/*x*/, reg_tohost/*x*/, reg_fromhost/*x*/,
reg_stats/*x*/, reg_fromhost/*x*/, reg_tohost/*x*/, reg_fromhost/*x*/,
reg_stats/*x*/, reg_fromhost/*x*/, reg_tohost/*x*/, reg_fromhost/*x*/,
reg_stats, reg_fromhost/*x*/, reg_tohost, reg_fromhost
)(addr)
when (wen) {
@@ -260,7 +242,7 @@ class PCR(implicit conf: RocketConfiguration) extends Module
reg_status.s64 := true
reg_status.u64 := true
reg_status.zero := 0
if (!conf.vec) reg_status.ev := false
if (conf.rocc.isEmpty) reg_status.er := false
if (!conf.fpu) reg_status.ef := false
}
when (addr === EPC) { reg_epc := wdata(VADDR_BITS,0).toSInt }
@@ -273,7 +255,6 @@ class PCR(implicit conf: RocketConfiguration) extends Module
when (addr === SUP0) { reg_sup0 := wdata; }
when (addr === SUP1) { reg_sup1 := wdata; }
when (addr === PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUInt; }
when (addr === VECBANK) { reg_vecbank:= wdata(7,0) }
when (addr === STATS) { reg_stats := wdata(0) }
}
@@ -284,7 +265,7 @@ class PCR(implicit conf: RocketConfiguration) extends Module
reg_status.ei := false
reg_status.pei := false
reg_status.ef := false
reg_status.ev := false
reg_status.er := false
reg_status.ps := false
reg_status.s := true
reg_status.u64 := true

186
rocket/src/main/scala/dpath_vec.scala
View File

@@ -1,186 +0,0 @@
package rocket
import Chisel._
import Node._
import Instructions._
import hwacha.Constants._
class DpathVecInterfaceIO extends Bundle
{
val vcmdq = Decoupled(Bits(width = SZ_VCMD))
val vximm1q = Decoupled(Bits(width = SZ_VIMM))
val vximm2q = Decoupled(Bits(width = SZ_VSTRIDE))
val vcntq = Decoupled(Bits(width = SZ_VLEN+1))
val vpfcmdq = Decoupled(Bits(width = SZ_VCMD))
val vpfximm1q = Decoupled(Bits(width = SZ_VIMM))
val vpfximm2q = Decoupled(Bits(width = SZ_VSTRIDE))
val vpfcntq = Decoupled(Bits(width = SZ_VLEN))
val evac_addr = Bits(OUTPUT, 64)
val irq_aux = Bits(INPUT, 64)
}
class DpathVecIO extends Bundle
{
val ctrl = (new CtrlDpathVecIO).flip
val iface = new DpathVecInterfaceIO
val valid = Bool(INPUT)
val inst = Bits(INPUT, 32)
val vecbank = Bits(INPUT, 8)
val vecbankcnt = UInt(INPUT, 4)
val wdata = Bits(INPUT, 64)
val rs2 = Bits(INPUT, 64)
val wen = Bool(OUTPUT)
val irq_aux = Bits(OUTPUT, 64)
val appvl = UInt(OUTPUT, 12)
val nxregs = UInt(OUTPUT, 6)
val nfregs = UInt(OUTPUT, 6)
}
class rocketDpathVec extends Module
{
val io = new DpathVecIO
val nxregs_stage = Mux(io.ctrl.fn === VEC_CFG, io.wdata(5,0), io.inst(15,10))
val nfregs_stage = Mux(io.ctrl.fn === VEC_CFG, io.rs2(5,0), io.inst(21,16))
val nxregs = Mux(nxregs_stage(5), Bits(32), Mux(nxregs_stage === Bits(0), Bits(1), nxregs_stage)) + UInt(0,7)
val nfregs = Mux(nfregs_stage(5), Bits(32), nfregs_stage) + UInt(0,7)
val nregs = nxregs + nfregs
//val uts_per_bank = UInt(4,9)
val nreg_mod_bank = MuxLookup(
nregs, UInt(4,9), Array(
UInt(0,7) -> UInt(256,9),
UInt(1,7) -> UInt(256,9),
UInt(2,7) -> UInt(256,9),
UInt(3,7) -> UInt(128,9),
UInt(4,7) -> UInt(85,9),
UInt(5,7) -> UInt(64,9),
UInt(6,7) -> UInt(51,9),
UInt(7,7) -> UInt(42,9),
UInt(8,7) -> UInt(36,9),
UInt(9,7) -> UInt(32,9),
UInt(10,7) -> UInt(28,9),
UInt(11,7) -> UInt(25,9),
UInt(12,7) -> UInt(23,9),
UInt(13,7) -> UInt(21,9),
UInt(14,7) -> UInt(19,9),
UInt(15,7) -> UInt(18,9),
UInt(16,7) -> UInt(17,9),
UInt(17,7) -> UInt(16,9),
UInt(18,7) -> UInt(15,9),
UInt(19,7) -> UInt(14,9),
UInt(20,7) -> UInt(13,9),
UInt(21,7) -> UInt(12,9),
UInt(22,7) -> UInt(12,9),
UInt(23,7) -> UInt(11,9),
UInt(24,7) -> UInt(11,9),
UInt(25,7) -> UInt(10,9),
UInt(26,7) -> UInt(10,9),
UInt(27,7) -> UInt(9,9),
UInt(28,7) -> UInt(9,9),
UInt(29,7) -> UInt(9,9),
UInt(30,7) -> UInt(8,9),
UInt(31,7) -> UInt(8,9),
UInt(32,7) -> UInt(8,9),
UInt(33,7) -> UInt(8,9),
UInt(34,7) -> UInt(7,9),
UInt(35,7) -> UInt(7,9),
UInt(36,7) -> UInt(7,9),
UInt(37,7) -> UInt(7,9),
UInt(38,7) -> UInt(6,9),
UInt(39,7) -> UInt(6,9),
UInt(40,7) -> UInt(6,9),
UInt(41,7) -> UInt(6,9),
UInt(42,7) -> UInt(6,9),
UInt(43,7) -> UInt(6,9),
UInt(44,7) -> UInt(5,9),
UInt(45,7) -> UInt(5,9),
UInt(46,7) -> UInt(5,9),
UInt(47,7) -> UInt(5,9),
UInt(48,7) -> UInt(5,9),
UInt(49,7) -> UInt(5,9),
UInt(50,7) -> UInt(5,9),
UInt(51,7) -> UInt(5,9),
UInt(52,7) -> UInt(5,9)
))
val max_threads = UInt(WIDTH_BMASK)
val uts_per_bank = Mux(Bool(HAVE_PVFB) & nreg_mod_bank > max_threads, max_threads, nreg_mod_bank)
val reg_hwvl = Reg(init=UInt(32, 12))
val reg_appvl0 = Reg(init=Bool(true))
val hwvl_vcfg = (uts_per_bank * io.vecbankcnt)(11,0)
val hwvl =
Mux(io.ctrl.fn === VEC_CFG || io.ctrl.fn === VEC_CFGVL, hwvl_vcfg,
reg_hwvl)
val appvl =
Mux(io.ctrl.fn === VEC_CFG, UInt(0),
Mux(io.wdata(11,0) < hwvl, io.wdata(11,0).toUInt,
hwvl.toUInt))
val reg_nxregs = Reg(init=UInt(32, 6))
val reg_nfregs = Reg(init=UInt(32, 6))
val reg_appvl = Reg(init=UInt(0, 12))
when (io.valid)
{
when (io.ctrl.fn === VEC_CFG || io.ctrl.fn === VEC_CFGVL)
{
reg_hwvl := hwvl_vcfg
reg_nxregs := nxregs
reg_nfregs := nfregs
}
when (io.ctrl.fn === VEC_VL || io.ctrl.fn === VEC_CFGVL)
{
reg_appvl0 := !(appvl.orR())
reg_appvl := appvl
}
}
io.wen := io.valid && io.ctrl.wen
io.irq_aux := io.iface.irq_aux
io.appvl := Mux(io.ctrl.fn === VEC_VL || io.ctrl.fn === VEC_CFGVL, appvl, reg_appvl)
io.nxregs := reg_nxregs
io.nfregs := reg_nfregs
val appvlm1 = appvl - UInt(1)
val waddr = io.inst(31,27)
val raddr1 = io.inst(26,22)
io.iface.vcmdq.bits :=
Mux(io.ctrl.sel_vcmd === VCMD_I, Cat(Bits(0,2), Bits(0,4), io.inst(9,8), Bits(0,6), Bits(0,6)),
Mux(io.ctrl.sel_vcmd === VCMD_F, Cat(Bits(0,2), Bits(1,3), io.inst(9,7), Bits(0,6), Bits(0,6)),
Mux(io.ctrl.sel_vcmd === VCMD_TX, Cat(Bits(1,2), io.inst(13,8), Bits(0,1), waddr, Bits(0,1), raddr1),
Mux(io.ctrl.sel_vcmd === VCMD_TF, Cat(Bits(1,2), io.inst(13,8), Bits(1,1), waddr, Bits(1,1), raddr1),
Mux(io.ctrl.sel_vcmd === VCMD_MX, Cat(Bits(1,1), io.inst(13,12), io.inst(2), io.inst(10,7), Bits(0,1), waddr, Bits(0,1), waddr),
Mux(io.ctrl.sel_vcmd === VCMD_MF, Cat(Bits(1,1), io.inst(13,12), io.inst(2), io.inst(10,7), Bits(1,1), waddr, Bits(1,1), waddr),
Mux(io.ctrl.sel_vcmd === VCMD_A, io.wdata(SZ_VCMD-1, 0),
Bits(0,20))))))))
io.iface.vximm1q.bits :=
Mux(io.ctrl.sel_vimm === VIMM_VLEN, Cat(Bits(0,29), io.vecbankcnt, io.vecbank, nfregs(5,0), nxregs(5,0), appvlm1(10,0)),
io.wdata) // VIMM_ALU
io.iface.vximm2q.bits :=
Mux(io.ctrl.sel_vimm2 === VIMM2_RS2, io.rs2,
io.wdata) // VIMM2_ALU
val last = io.rs2(1)
io.iface.vcntq.bits := Cat(last, io.iface.vpfcntq.bits)
io.iface.vpfcmdq.bits := io.iface.vcmdq.bits
io.iface.vpfximm1q.bits := io.iface.vximm1q.bits
io.iface.vpfximm2q.bits := io.iface.vximm2q.bits
io.iface.vpfcntq.bits := io.wdata(SZ_VLEN-1, 0)
io.iface.evac_addr := io.wdata
io.ctrl.inst := io.inst
io.ctrl.appvl0 := reg_appvl0
io.ctrl.pfq := io.rs2(0)
}

152
rocket/src/main/scala/instructions.scala
View File

@@ -167,87 +167,30 @@ object Instructions
def FNMSUB_D = Bits("b???????????????????????011001011")
def FNMADD_D = Bits("b???????????????????????011001111")
/* Automatically generated by parse-opcodes */
def STOP = Bits("b00000000000000000000001011110111")
def UTIDX = Bits("b?????000000000000000001101110111")
def MOVZ = Bits("b???????????????00000001111110111")
def MOVN = Bits("b???????????????00000011111110111")
def FMOVZ = Bits("b???????????????00000101111110111")
def FMOVN = Bits("b???????????????00000111111110111")
def VSETCFGVL = Bits("b??????????????????????1110001011")
def VSETVL = Bits("b??????????0000000000001100001011")
def VMVV = Bits("b??????????0000000000011100001011")
def VGETCFG = Bits("b?????000000000000000001000001011")
def VGETVL = Bits("b?????000000000000000011000001011")
def VF = Bits("b??????????00000???????0100001011")
def VXCPTSAVE = Bits("b00000?????0000000000000110001011")
def VXCPTRESTORE = Bits("b00000?????0000000000010110001011")
def VXCPTKILL = Bits("b00000000000000000000100110001011")
def VXCPTEVAC = Bits("b00000?????0000000000110110001011")
def VXCPTHOLD = Bits("b00000000000000000001000110001011")
def VENQCMD = Bits("b00000??????????00001010110001011")
def VENQIMM1 = Bits("b00000??????????00001100110001011")
def VENQIMM2 = Bits("b00000??????????00001110110001011")
def VENQCNT = Bits("b00000??????????00010000110001011")
def VLD = Bits("b??????????0000000000110100001111")
def VLW = Bits("b??????????0000000000100100001111")
def VLWU = Bits("b??????????0000000001100100001111")
def VLH = Bits("b??????????0000000000010100001111")
def VLHU = Bits("b??????????0000000001010100001111")
def VLB = Bits("b??????????0000000000000100001111")
def VLBU = Bits("b??????????0000000001000100001111")
def VFLD = Bits("b??????????0000000010110100001111")
def VFLW = Bits("b??????????0000000010100100001111")
def VLSTD = Bits("b???????????????00000110110001111")
def VLSTW = Bits("b???????????????00000100110001111")
def VLSTWU = Bits("b???????????????00001100110001111")
def VLSTH = Bits("b???????????????00000010110001111")
def VLSTHU = Bits("b???????????????00001010110001111")
def VLSTB = Bits("b???????????????00000000110001111")
def VLSTBU = Bits("b???????????????00001000110001111")
def VFLSTD = Bits("b???????????????00010110110001111")
def VFLSTW = Bits("b???????????????00010100110001111")
def VLSEGD = Bits("b??????????00000???00110101011011")
def VLSEGW = Bits("b??????????00000???00100101011011")
def VLSEGWU = Bits("b??????????00000???01100101011011")
def VLSEGH = Bits("b??????????00000???00010101011011")
def VLSEGHU = Bits("b??????????00000???01010101011011")
def VLSEGB = Bits("b??????????00000???00000101011011")
def VLSEGBU = Bits("b??????????00000???01000101011011")
def VFLSEGD = Bits("b??????????00000???10110101011011")
def VFLSEGW = Bits("b??????????00000???10100101011011")
def VLSEGSTD = Bits("b??????????????????00110111011011")
def VLSEGSTW = Bits("b??????????????????00100111011011")
def VLSEGSTWU = Bits("b??????????????????01100111011011")
def VLSEGSTH = Bits("b??????????????????00010111011011")
def VLSEGSTHU = Bits("b??????????????????01010111011011")
def VLSEGSTB = Bits("b??????????????????00000111011011")
def VLSEGSTBU = Bits("b??????????????????01000111011011")
def VFLSEGSTD = Bits("b??????????00000???10110111011011")
def VFLSEGSTW = Bits("b??????????00000???10100111011011")
def VSD = Bits("b??????????0000010000110100001111")
def VSW = Bits("b??????????0000010000100100001111")
def VSH = Bits("b??????????0000010000010100001111")
def VSB = Bits("b??????????0000010000000100001111")
def VFSD = Bits("b??????????0000010010110100001111")
def VFSW = Bits("b??????????0000010010100100001111")
def VSSTD = Bits("b???????????????10000110110001111")
def VSSTW = Bits("b???????????????10000100110001111")
def VSSTH = Bits("b???????????????10000010110001111")
def VSSTB = Bits("b???????????????10000000110001111")
def VFSSTD = Bits("b???????????????10010110110001111")
def VFSSTW = Bits("b???????????????10010100110001111")
def VSSEGD = Bits("b??????????00000???00110101111011")
def VSSEGW = Bits("b??????????00000???00100101111011")
def VSSEGH = Bits("b??????????00000???00010101111011")
def VSSEGB = Bits("b??????????00000???00000101111011")
def VFSSEGD = Bits("b??????????00000???10110101111011")
def VFSSEGW = Bits("b??????????00000???10100101111011")
def VSSEGSTD = Bits("b??????????????????00110111111011")
def VSSEGSTW = Bits("b??????????????????00100111111011")
def VSSEGSTH = Bits("b??????????????????00010111111011")
def VSSEGSTB = Bits("b??????????????????00000111111011")
def VFSSEGSTD = Bits("b??????????00000???10110111111011")
def VFSSEGSTW = Bits("b??????????00000???10100111111011")
def CUSTOM0 = Bits("b??????????????????????0000001011")
def CUSTOM0_RS1 = Bits("b??????????????????????0100001011")
def CUSTOM0_RS1_RS2 = Bits("b??????????????????????0110001011")
def CUSTOM0_RD = Bits("b??????????????????????1000001011")
def CUSTOM0_RD_RS1 = Bits("b??????????????????????1100001011")
def CUSTOM0_RD_RS1_RS2 = Bits("b??????????????????????1110001011")
def CUSTOM1 = Bits("b??????????????????????0000001111")
def CUSTOM1_RS1 = Bits("b??????????????????????0100001111")
def CUSTOM1_RS1_RS2 = Bits("b??????????????????????0110001111")
def CUSTOM1_RD = Bits("b??????????????????????1000001111")
def CUSTOM1_RD_RS1 = Bits("b??????????????????????1100001111")
def CUSTOM1_RD_RS1_RS2 = Bits("b??????????????????????1110001111")
def CUSTOM2 = Bits("b??????????????????????0001010111")
def CUSTOM2_RS1 = Bits("b??????????????????????0101010111")
def CUSTOM2_RS1_RS2 = Bits("b??????????????????????0111010111")
def CUSTOM2_RD = Bits("b??????????????????????1001010111")
def CUSTOM2_RD_RS1 = Bits("b??????????????????????1101010111")
def CUSTOM2_RD_RS1_RS2 = Bits("b??????????????????????1111010111")
def CUSTOM3 = Bits("b??????????????????????0001111011")
def CUSTOM3_RS1 = Bits("b??????????????????????0101111011")
def CUSTOM3_RS1_RS2 = Bits("b??????????????????????0111111011")
def CUSTOM3_RD = Bits("b??????????????????????1001111011")
def CUSTOM3_RD_RS1 = Bits("b??????????????????????1101111011")
def CUSTOM3_RD_RS1_RS2 = Bits("b??????????????????????1111111011")
}
object Disassemble
@@ -511,51 +454,6 @@ object Disassemble
FLW-> List(Str("flw "), FMT_FLD),
FLD-> List(Str("fld "), FMT_FLD),
FSW-> List(Str("fsw "), FMT_FST),
FSD-> List(Str("fsd "), FMT_FST),
VSETCFGVL-> List(Str("vecInst "), FMT_0),
VSETVL-> List(Str("vecInst "), FMT_0),
VF-> List(Str("vecInst "), FMT_0),
VMVV-> List(Str("vecInst "), FMT_0),
FENCE_V_L-> List(Str("vecInst "), FMT_0),
FENCE_V_G-> List(Str("vecInst "), FMT_0),
VLD-> List(Str("vecInst "), FMT_0),
VLW-> List(Str("vecInst "), FMT_0),
VLWU-> List(Str("vecInst "), FMT_0),
VLH-> List(Str("vecInst "), FMT_0),
VLHU-> List(Str("vecInst "), FMT_0),
VLB-> List(Str("vecInst "), FMT_0),
VLBU-> List(Str("vecInst "), FMT_0),
VSD-> List(Str("vecInst "), FMT_0),
VSW-> List(Str("vecInst "), FMT_0),
VSH-> List(Str("vecInst "), FMT_0),
VSB-> List(Str("vecInst "), FMT_0),
VFLD-> List(Str("vecInst "), FMT_0),
VFLW-> List(Str("vecInst "), FMT_0),
VFSD-> List(Str("vecInst "), FMT_0),
VFSW-> List(Str("vecInst "), FMT_0),
VLSTD-> List(Str("vecInst "), FMT_0),
VLSTW-> List(Str("vecInst "), FMT_0),
VLSTWU-> List(Str("vecInst "), FMT_0),
VLSTH-> List(Str("vecInst "), FMT_0),
VLSTHU-> List(Str("vecInst "), FMT_0),
VLSTB-> List(Str("vecInst "), FMT_0),
VLSTBU-> List(Str("vecInst "), FMT_0),
VSSTD-> List(Str("vecInst "), FMT_0),
VSSTW-> List(Str("vecInst "), FMT_0),
VSSTH-> List(Str("vecInst "), FMT_0),
VSSTB-> List(Str("vecInst "), FMT_0),
VFLSTD-> List(Str("vecInst "), FMT_0),
VFLSTW-> List(Str("vecInst "), FMT_0),
VFSSTD-> List(Str("vecInst "), FMT_0),
VFSSTW-> List(Str("vecInst "), FMT_0),
VENQCMD-> List(Str("vecInst "), FMT_0),
VENQIMM1-> List(Str("vecInst "), FMT_0),
VENQIMM2-> List(Str("vecInst "), FMT_0),
VENQCNT-> List(Str("vecInst "), FMT_0),
VXCPTEVAC-> List(Str("vecInst "), FMT_0),
VXCPTKILL-> List(Str("vecInst "), FMT_0),
VXCPTHOLD-> List(Str("vecInst "), FMT_0)
FSD-> List(Str("fsd "), FMT_FST)
)
}

1
rocket/src/main/scala/nbdcache.scala
View File

@@ -69,7 +69,6 @@ class RandomReplacement(implicit conf: DCacheConfig) extends ReplacementPolicy
object StoreGen
{
def apply(r: HellaCacheReq) = new StoreGen(r.typ, r.addr, r.data)
def apply(r: hwacha.io_dmem_req_bundle) = new StoreGen(r.typ, r.addr, r.data)
def apply(typ: Bits, addr: Bits, data: Bits = Bits(0)) = new StoreGen(typ, addr, data)
}

6
rocket/src/main/scala/rocc.scala Normal file
View File

@@ -0,0 +1,6 @@
package rocket
import Chisel._
import Node._
abstract class RoCC extends Module

33
rocket/src/main/scala/tile.scala
View File

@@ -6,7 +6,7 @@ import Util._
case class RocketConfiguration(tl: TileLinkConfiguration,
icache: ICacheConfig, dcache: DCacheConfig,
fpu: Boolean, vec: Boolean,
fpu: Boolean, rocc: Option[RoCC] = None,
fastLoadWord: Boolean = true,
fastLoadByte: Boolean = false,
fastMulDiv: Boolean = true)
@@ -20,7 +20,7 @@ case class RocketConfiguration(tl: TileLinkConfiguration,
class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module(_reset = resetSignal) with ClientCoherenceAgent
{
val memPorts = 2 + confIn.vec
val memPorts = 2
val dcachePortId = 0
val icachePortId = 1
val vicachePortId = 2
@@ -38,14 +38,23 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module
val core = Module(new Core)
val icache = Module(new Frontend)
val dcache = Module(new HellaCache)
val ptw = Module(new PTW(2))
val arbiter = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(memPorts))
arbiter.io.in(dcachePortId) <> dcache.io.mem
arbiter.io.in(icachePortId) <> icache.io.mem
val dcacheArb = Module(new HellaCacheArbiter(2 + !conf.rocc.isEmpty))
dcacheArb.io.requestor(0) <> ptw.io.mem
dcacheArb.io.requestor(1) <> core.io.dmem
dcache.io.cpu <> dcacheArb.io.mem
io.tilelink.acquire <> arbiter.io.out.acquire
arbiter.io.out.grant <> io.tilelink.grant
io.tilelink.grant_ack <> arbiter.io.out.grant_ack
ptw.io.requestor(0) <> icache.io.cpu.ptw
ptw.io.requestor(1) <> dcache.io.cpu.ptw
val memArb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(memPorts))
memArb.io.in(dcachePortId) <> dcache.io.mem
memArb.io.in(icachePortId) <> icache.io.mem
io.tilelink.acquire <> memArb.io.out.acquire
memArb.io.out.grant <> io.tilelink.grant
io.tilelink.grant_ack <> memArb.io.out.grant_ack
dcache.io.mem.probe <> io.tilelink.probe
io.tilelink.release.data <> dcache.io.mem.release.data
io.tilelink.release.meta.valid := dcache.io.mem.release.meta.valid
@@ -53,13 +62,7 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module
io.tilelink.release.meta.bits := dcache.io.mem.release.meta.bits
io.tilelink.release.meta.bits.payload.client_xact_id := Cat(dcache.io.mem.release.meta.bits.payload.client_xact_id, UInt(dcachePortId, log2Up(memPorts))) // Mimic client id extension done by UncachedTileLinkIOArbiter for Acquires from either client)
if (conf.vec) {
val vicache = Module(new Frontend()(ICacheConfig(128, 1), tlConf)) // 128 sets x 1 ways (8KB)
arbiter.io.in(vicachePortId) <> vicache.io.mem
core.io.vimem <> vicache.io.cpu
}
core.io.host <> io.host
core.io.imem <> icache.io.cpu
core.io.dmem <> dcache.io.cpu
core.io.ptw <> ptw.io.dpath
}