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coreplex: fix BankedL2 line width

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Wesley W. Terpstra 2016-11-04 11:18:31 -07:00 committed by Henry Cook
parent ea602790a8
commit d03046d11c
2 changed files with 2 additions and 2 deletions
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2
src/main/scala/coreplex/BaseCoreplex.scala
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@ -99,7 +99,7 @@ trait CoreplexNetworkModule extends HasCoreplexParameters {
trait BankedL2 { trait BankedL2 {
this: CoreplexNetwork => this: CoreplexNetwork =>
require (isPow2(nBanksPerMemChannel)) require (isPow2(nBanksPerMemChannel))
require (isPow2(l1tol2_beatBytes)) require (isPow2(l1tol2_lineBytes))
def l2ManagerFactory(): (TLInwardNode, TLOutwardNode) def l2ManagerFactory(): (TLInwardNode, TLOutwardNode)

2
src/main/scala/coreplex/Coreplex.scala
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@ -13,7 +13,7 @@ import rocket._
trait BroadcastL2 { trait BroadcastL2 {
this: CoreplexNetwork => this: CoreplexNetwork =>
def l2ManagerFactory() = { def l2ManagerFactory() = {
val bh = LazyModule(new TLBroadcast(l1tol2_beatBytes, nTrackersPerBank)) val bh = LazyModule(new TLBroadcast(l1tol2_lineBytes, nTrackersPerBank))
(bh.node, bh.node) (bh.node, bh.node)
} }
} }