From d03046d11c484b501b07e5d65aceb3c847808c90 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 4 Nov 2016 11:18:31 -0700 Subject: [PATCH] coreplex: fix BankedL2 line width --- src/main/scala/coreplex/BaseCoreplex.scala | 2 +- src/main/scala/coreplex/Coreplex.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala index 009a1464..f452fda5 100644 --- a/src/main/scala/coreplex/BaseCoreplex.scala +++ b/src/main/scala/coreplex/BaseCoreplex.scala @@ -99,7 +99,7 @@ trait CoreplexNetworkModule extends HasCoreplexParameters { trait BankedL2 { this: CoreplexNetwork => require (isPow2(nBanksPerMemChannel)) - require (isPow2(l1tol2_beatBytes)) + require (isPow2(l1tol2_lineBytes)) def l2ManagerFactory(): (TLInwardNode, TLOutwardNode) diff --git a/src/main/scala/coreplex/Coreplex.scala b/src/main/scala/coreplex/Coreplex.scala index 0e5d2a1e..c9fa0429 100644 --- a/src/main/scala/coreplex/Coreplex.scala +++ b/src/main/scala/coreplex/Coreplex.scala @@ -13,7 +13,7 @@ import rocket._ trait BroadcastL2 { this: CoreplexNetwork => def l2ManagerFactory() = { - val bh = LazyModule(new TLBroadcast(l1tol2_beatBytes, nTrackersPerBank)) + val bh = LazyModule(new TLBroadcast(l1tol2_lineBytes, nTrackersPerBank)) (bh.node, bh.node) } }