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coreplex: fix BankedL2 line width

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This commit is contained in:
Wesley W. Terpstra
2016-11-04 11:18:31 -07:00
committed by Henry Cook
parent ea602790a8
commit d03046d11c
2 changed files with 2 additions and 2 deletions
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src/main/scala/coreplex/BaseCoreplex.scala
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@ -99,7 +99,7 @@ trait CoreplexNetworkModule extends HasCoreplexParameters {
trait BankedL2 {
this: CoreplexNetwork =>
require (isPow2(nBanksPerMemChannel))
require (isPow2(l1tol2_beatBytes))
require (isPow2(l1tol2_lineBytes))
def l2ManagerFactory(): (TLInwardNode, TLOutwardNode)