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coreplex: fix BankedL2 line width

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Wesley W. Terpstra authored and Henry Cook committed 2016-11-04 13:35:36 -07:00
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commit d03046d11c
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src/main/scala/coreplex/BaseCoreplex.scala
+1 -1
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@@ -99,7 +99,7 @@ trait CoreplexNetworkModule extends HasCoreplexParameters {
trait BankedL2 {
this: CoreplexNetwork =>
require (isPow2(nBanksPerMemChannel))
require (isPow2(l1tol2_beatBytes))
require (isPow2(l1tol2_lineBytes))
def l2ManagerFactory(): (TLInwardNode, TLOutwardNode)