riscv/rocket-chip
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decouple all interfaces between tile and top

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also, add an "incoherent" bit to tilelink to indicate no probes needed
This commit is contained in:
Andrew Waterman 2012-07-17 22:55:00 -07:00
parent a79747a062
commit d01e70c672
2 changed files with 18 additions and 9 deletions
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10
uncore/llc.scala
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@ -107,7 +107,7 @@ class LLCMSHRFile(sets: Int, ways: Int, outstanding: Int) extends Component
val addr = UFix(width = PADDR_BITS - OFFSET_BITS) val addr = UFix(width = PADDR_BITS - OFFSET_BITS)
val way = UFix(width = log2Up(ways)) val way = UFix(width = log2Up(ways))
} } } }
val mem = new ioMem val mem = new ioMemPipe
val mem_resp_set = UFix(OUTPUT, log2Up(sets)) val mem_resp_set = UFix(OUTPUT, log2Up(sets))
val mem_resp_way = UFix(OUTPUT, log2Up(ways)) val mem_resp_way = UFix(OUTPUT, log2Up(ways))
} }
@ -194,7 +194,7 @@ class LLCWriteback(requestors: Int) extends Component
val io = new Bundle { val io = new Bundle {
val req = Vec(requestors) { (new FIFOIO) { UFix(width = PADDR_BITS - OFFSET_BITS) }.flip } val req = Vec(requestors) { (new FIFOIO) { UFix(width = PADDR_BITS - OFFSET_BITS) }.flip }
val data = Vec(requestors) { (new FIFOIO) { new MemData }.flip } val data = Vec(requestors) { (new FIFOIO) { new MemData }.flip }
val mem = new ioMem val mem = new ioMemPipe
} }
val valid = Reg(resetVal = Bool(false)) val valid = Reg(resetVal = Bool(false))
@ -245,7 +245,7 @@ class LLCData(sets: Int, ways: Int, leaf: Mem[Bits]) extends Component
val req_data = (new FIFOIO) { new MemData }.flip val req_data = (new FIFOIO) { new MemData }.flip
val writeback = (new FIFOIO) { UFix(width = PADDR_BITS - OFFSET_BITS) } val writeback = (new FIFOIO) { UFix(width = PADDR_BITS - OFFSET_BITS) }
val writeback_data = (new FIFOIO) { new MemData } val writeback_data = (new FIFOIO) { new MemData }
val resp = (new PipeIO) { new MemResp } val resp = (new FIFOIO) { new MemResp }
val mem_resp = (new PipeIO) { new MemResp }.flip val mem_resp = (new PipeIO) { new MemResp }.flip
val mem_resp_set = UFix(INPUT, log2Up(sets)) val mem_resp_set = UFix(INPUT, log2Up(sets))
val mem_resp_way = UFix(INPUT, log2Up(ways)) val mem_resp_way = UFix(INPUT, log2Up(ways))
@ -298,7 +298,7 @@ class LLCData(sets: Int, ways: Int, leaf: Mem[Bits]) extends Component
io.writeback.valid := io.req.valid && io.req.ready && io.req.bits.isWriteback io.writeback.valid := io.req.valid && io.req.ready && io.req.bits.isWriteback
io.writeback.bits := io.req.bits.addr io.writeback.bits := io.req.bits.addr
q.io.deq.ready := Mux(q.io.deq.bits.isWriteback, io.writeback_data.ready, Bool(true)) q.io.deq.ready := Mux(q.io.deq.bits.isWriteback, io.writeback_data.ready, io.resp.ready)
io.resp.valid := q.io.deq.valid && !q.io.deq.bits.isWriteback io.resp.valid := q.io.deq.valid && !q.io.deq.bits.isWriteback
io.resp.bits := q.io.deq.bits io.resp.bits := q.io.deq.bits
io.writeback_data.valid := q.io.deq.valid && q.io.deq.bits.isWriteback io.writeback_data.valid := q.io.deq.valid && q.io.deq.bits.isWriteback
@ -309,7 +309,7 @@ class DRAMSideLLC(sets: Int, ways: Int, outstanding: Int, tagLeaf: Mem[Bits], da
{ {
val io = new Bundle { val io = new Bundle {
val cpu = new ioMem().flip val cpu = new ioMem().flip
val mem = new ioMem val mem = new ioMemPipe
} }
val tagWidth = PADDR_BITS - OFFSET_BITS - log2Up(sets) val tagWidth = PADDR_BITS - OFFSET_BITS - log2Up(sets)

17
uncore/uncore.scala
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@ -20,6 +20,13 @@ class MemResp () extends MemData
} }
class ioMem() extends Bundle class ioMem() extends Bundle
{
val req_cmd = (new FIFOIO) { new MemReqCmd() }
val req_data = (new FIFOIO) { new MemData() }
val resp = (new FIFOIO) { new MemResp() }.flip
}
class ioMemPipe() extends Bundle
{ {
val req_cmd = (new FIFOIO) { new MemReqCmd() } val req_cmd = (new FIFOIO) { new MemReqCmd() }
val req_data = (new FIFOIO) { new MemData() } val req_data = (new FIFOIO) { new MemData() }
@ -46,8 +53,9 @@ class ioTileLink extends Bundle {
val probe_req = (new FIFOIO) { new ProbeRequest }.flip val probe_req = (new FIFOIO) { new ProbeRequest }.flip
val probe_rep = (new FIFOIO) { new ProbeReply } val probe_rep = (new FIFOIO) { new ProbeReply }
val probe_rep_data = (new FIFOIO) { new ProbeReplyData } val probe_rep_data = (new FIFOIO) { new ProbeReplyData }
val xact_rep = (new PipeIO) { new TransactionReply }.flip val xact_rep = (new FIFOIO) { new TransactionReply }.flip
val xact_finish = (new FIFOIO) { new TransactionFinish } val xact_finish = (new FIFOIO) { new TransactionFinish }
val incoherent = Bool(OUTPUT)
} }
class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component { class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
@ -58,6 +66,7 @@ class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
val xact_finish = Bool(INPUT) val xact_finish = Bool(INPUT)
val p_rep_cnt_dec = Bits(INPUT, ntiles) val p_rep_cnt_dec = Bits(INPUT, ntiles)
val p_req_cnt_inc = Bits(INPUT, ntiles) val p_req_cnt_inc = Bits(INPUT, ntiles)
val tile_incoherent = Bits(INPUT, ntiles)
val p_rep_data = (new PipeIO) { new ProbeReplyData }.flip val p_rep_data = (new PipeIO) { new ProbeReplyData }.flip
val x_init_data = (new PipeIO) { new TransactionInitData }.flip val x_init_data = (new PipeIO) { new TransactionInitData }.flip
val sent_x_rep_ack = Bool(INPUT) val sent_x_rep_ack = Bool(INPUT)
@ -169,7 +178,7 @@ class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
tile_xact_id_ := io.alloc_req.bits.xact_init.tile_xact_id tile_xact_id_ := io.alloc_req.bits.xact_init.tile_xact_id
x_init_data_needs_write := co.messageHasData(io.alloc_req.bits.xact_init) x_init_data_needs_write := co.messageHasData(io.alloc_req.bits.xact_init)
x_needs_read := co.needsMemRead(io.alloc_req.bits.xact_init.x_type, UFix(0)) x_needs_read := co.needsMemRead(io.alloc_req.bits.xact_init.x_type, UFix(0))
val p_req_initial_flags = ~( UFix(1) << io.alloc_req.bits.tile_id ) //TODO: Broadcast only val p_req_initial_flags = ~(io.tile_incoherent | UFixToOH(io.alloc_req.bits.tile_id)) //TODO: Broadcast only
p_req_flags := p_req_initial_flags(ntiles-1,0) p_req_flags := p_req_initial_flags(ntiles-1,0)
mem_cnt := UFix(0) mem_cnt := UFix(0)
p_w_mem_cmd_sent := Bool(false) p_w_mem_cmd_sent := Bool(false)
@ -310,6 +319,7 @@ class CoherenceHubBroadcast(ntiles: Int, co: CoherencePolicy) extends CoherenceH
t.p_data.valid := p_data_valid_arr(i) t.p_data.valid := p_data_valid_arr(i)
t.p_rep_cnt_dec := p_rep_cnt_dec_arr(i).toBits t.p_rep_cnt_dec := p_rep_cnt_dec_arr(i).toBits
t.p_req_cnt_inc := p_req_cnt_inc_arr(i).toBits t.p_req_cnt_inc := p_req_cnt_inc_arr(i).toBits
t.tile_incoherent := (Vec(io.tiles.map(_.incoherent)) { Bool() }).toBits
t.sent_x_rep_ack := sent_x_rep_ack_arr(i) t.sent_x_rep_ack := sent_x_rep_ack_arr(i)
do_free_arr(i) := Bool(false) do_free_arr(i) := Bool(false)
sent_x_rep_ack_arr(i) := Bool(false) sent_x_rep_ack_arr(i) := Bool(false)
@ -360,8 +370,7 @@ class CoherenceHubBroadcast(ntiles: Int, co: CoherencePolicy) extends CoherenceH
} }
} }
} }
// If there were a ready signal due to e.g. intervening network use: io.mem.resp.ready := io.tiles(init_tile_id_arr(mem_idx)).xact_rep.ready
//io.mem.resp.ready := io.tiles(init_tile_id_arr.read(mem_idx)).xact_rep.ready
// Create an arbiter for the one memory port // Create an arbiter for the one memory port
// We have to arbitrate between the different trackers' memory requests // We have to arbitrate between the different trackers' memory requests