riscv/rocket-chip
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patches to make FAME1/dram IOs compile with up-to-date chisel (bumped)

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This commit is contained in:
Henry Cook
2014-04-21 17:26:33 -07:00
parent 1bf5439f0b
commit cfd6748318
2 changed files with 4 additions and 4 deletions
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2
chisel

Submodule chisel updated: 41d48485e1...60fb4c60ed

6
src/main/scala/fpga.scala
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@@ -185,9 +185,9 @@ class FPGATop extends Module {
referenceChip.DecoupledIOs("host_out").target.ready := io.host.out.ready
referenceChip.DecoupledIOs("host_out").host_ready := Bool(true)
io.host.clk := referenceChip.DebugIOs("host_clk")
io.host.clk_edge := referenceChip.DebugIOs("host_clk_edge")
io.host.debug_stats_pcr := referenceChip.DebugIOs("host_debug_stats_pcr")
io.host.clk := referenceChip.DebugIOs("host_clk").toBits()(0)
io.host.clk_edge := referenceChip.DebugIOs("host_clk_edge").toBits()(0)
io.host.debug_stats_pcr := referenceChip.DebugIOs("host_debug_stats_pcr").toBits()(0)
//reference chip to dram model connections
val mem_req_cmd_queue = Module(new FameQueue(8)(new MemReqCmd()))