From cfd6748318792b01c23a25b554d50cc0ed1dce14 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 21 Apr 2014 17:26:33 -0700 Subject: [PATCH] patches to make FAME1/dram IOs compile with up-to-date chisel (bumped) --- chisel | 2 +- src/main/scala/fpga.scala | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/chisel b/chisel index 41d48485..60fb4c60 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit 41d48485e1cd454e5b7966a6efaac63ba5656796 +Subproject commit 60fb4c60ed0184a5acdaa32535ac417bd691b4c4 diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala index ae82bc2b..79203e40 100644 --- a/src/main/scala/fpga.scala +++ b/src/main/scala/fpga.scala @@ -185,9 +185,9 @@ class FPGATop extends Module { referenceChip.DecoupledIOs("host_out").target.ready := io.host.out.ready referenceChip.DecoupledIOs("host_out").host_ready := Bool(true) - io.host.clk := referenceChip.DebugIOs("host_clk") - io.host.clk_edge := referenceChip.DebugIOs("host_clk_edge") - io.host.debug_stats_pcr := referenceChip.DebugIOs("host_debug_stats_pcr") + io.host.clk := referenceChip.DebugIOs("host_clk").toBits()(0) + io.host.clk_edge := referenceChip.DebugIOs("host_clk_edge").toBits()(0) + io.host.debug_stats_pcr := referenceChip.DebugIOs("host_debug_stats_pcr").toBits()(0) //reference chip to dram model connections val mem_req_cmd_queue = Module(new FameQueue(8)(new MemReqCmd()))