patches to make FAME1/dram IOs compile with up-to-date chisel (bumped)
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parent
1bf5439f0b
commit
cfd6748318
2
chisel
2
chisel
@ -1 +1 @@
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Subproject commit 41d48485e1cd454e5b7966a6efaac63ba5656796
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Subproject commit 60fb4c60ed0184a5acdaa32535ac417bd691b4c4
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@ -185,9 +185,9 @@ class FPGATop extends Module {
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referenceChip.DecoupledIOs("host_out").target.ready := io.host.out.ready
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referenceChip.DecoupledIOs("host_out").target.ready := io.host.out.ready
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referenceChip.DecoupledIOs("host_out").host_ready := Bool(true)
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referenceChip.DecoupledIOs("host_out").host_ready := Bool(true)
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io.host.clk := referenceChip.DebugIOs("host_clk")
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io.host.clk := referenceChip.DebugIOs("host_clk").toBits()(0)
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io.host.clk_edge := referenceChip.DebugIOs("host_clk_edge")
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io.host.clk_edge := referenceChip.DebugIOs("host_clk_edge").toBits()(0)
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io.host.debug_stats_pcr := referenceChip.DebugIOs("host_debug_stats_pcr")
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io.host.debug_stats_pcr := referenceChip.DebugIOs("host_debug_stats_pcr").toBits()(0)
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//reference chip to dram model connections
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//reference chip to dram model connections
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val mem_req_cmd_queue = Module(new FameQueue(8)(new MemReqCmd()))
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val mem_req_cmd_queue = Module(new FameQueue(8)(new MemReqCmd()))
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