riscv/rocket-chip
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rocketchip: add blind ports to DTS

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Wesley W. Terpstra committed 2017-03-02 21:19:22 -08:00
1 parent 9a5e2e038b
commit cfd367248f
8 files changed
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src/main/scala/uncore/tilelink2/ToAXI4.scala
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@@ -23,6 +23,7 @@ case class TLToAXI4Node(idBits: Int) extends MixedAdapterNode(TLImp, AXI4Imp)(
managers = p.slaves.map { case s =>
TLManagerParameters(
address = s.address,
resources = s.resources,
regionType = s.regionType,
executable = s.executable,
nodePath = s.nodePath,