riscv/rocket-chip
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rocketchip: add blind ports to DTS

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This commit is contained in:
Wesley W. Terpstra
2017-03-01 00:03:01 -08:00
parent 9a5e2e038b
commit cfd367248f
8 changed files with 21 additions and 1 deletions
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1
src/main/scala/uncore/tilelink2/ToAHB.scala
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@ -19,6 +19,7 @@ case class TLToAHBNode() extends MixedAdapterNode(TLImp, AHBImp)(
val managers = slaves.map { case s =>
TLManagerParameters(
address = s.address,
resources = s.resources,
regionType = s.regionType,
executable = s.executable,
nodePath = s.nodePath,

1
src/main/scala/uncore/tilelink2/ToAPB.scala
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@ -19,6 +19,7 @@ case class TLToAPBNode() extends MixedAdapterNode(TLImp, APBImp)(
val managers = slaves.map { case s =>
TLManagerParameters(
address = s.address,
resources = s.resources,
regionType = s.regionType,
executable = s.executable,
nodePath = s.nodePath,

1
src/main/scala/uncore/tilelink2/ToAXI4.scala
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@ -23,6 +23,7 @@ case class TLToAXI4Node(idBits: Int) extends MixedAdapterNode(TLImp, AXI4Imp)(
managers = p.slaves.map { case s =>
TLManagerParameters(
address = s.address,
resources = s.resources,
regionType = s.regionType,
executable = s.executable,
nodePath = s.nodePath,