rocketchip: add blind ports to DTS

src/main/scala/uncore/ahb/Parameters.scala

@@ -9,6 +9,7 @@ import scala.math.max
 
 case class AHBSlaveParameters(
   address:       Seq[AddressSet],
+  resources:     Seq[Resource] = Nil,
   regionType:    RegionType.T  = RegionType.GET_EFFECTS,
   executable:    Boolean       = false, // processor can execute from this memory
   nodePath:      Seq[BaseNode] = Seq(),

src/main/scala/uncore/apb/Parameters.scala

@@ -9,6 +9,7 @@ import scala.math.max
 
 case class APBSlaveParameters(
   address:       Seq[AddressSet],
+  resources:     Seq[Resource] = Nil,
   regionType:    RegionType.T  = RegionType.GET_EFFECTS,
   executable:    Boolean       = false, // processor can execute from this memory
   nodePath:      Seq[BaseNode] = Seq(),

src/main/scala/uncore/axi4/Parameters.scala

@@ -9,6 +9,7 @@ import scala.math.max
 
 case class AXI4SlaveParameters(
   address:       Seq[AddressSet],
+  resources:     Seq[Resource] = Nil,
   regionType:    RegionType.T  = RegionType.GET_EFFECTS,
   executable:    Boolean       = false, // processor can execute from this memory
   nodePath:      Seq[BaseNode] = Seq(),

src/main/scala/uncore/axi4/ToTL.scala

@@ -20,6 +20,7 @@ case class AXI4ToTLNode() extends MixedAdapterNode(AXI4Imp, TLImp)(
     slaves = mp.managers.map { m =>
       AXI4SlaveParameters(
         address       = m.address,
+        resources     = m.resources,
         regionType    = m.regionType,
         executable    = m.executable,
         nodePath      = m.nodePath,

src/main/scala/uncore/tilelink2/ToAHB.scala

@@ -19,6 +19,7 @@ case class TLToAHBNode() extends MixedAdapterNode(TLImp, AHBImp)(
     val managers = slaves.map { case s =>
       TLManagerParameters(
         address            = s.address,
+        resources          = s.resources,
         regionType         = s.regionType,
         executable         = s.executable,
         nodePath           = s.nodePath,

src/main/scala/uncore/tilelink2/ToAPB.scala

@@ -19,6 +19,7 @@ case class TLToAPBNode() extends MixedAdapterNode(TLImp, APBImp)(
     val managers = slaves.map { case s =>
       TLManagerParameters(
         address            = s.address,
+        resources          = s.resources,
         regionType         = s.regionType,
         executable         = s.executable,
         nodePath           = s.nodePath,

src/main/scala/uncore/tilelink2/ToAXI4.scala

@@ -23,6 +23,7 @@ case class TLToAXI4Node(idBits: Int) extends MixedAdapterNode(TLImp, AXI4Imp)(
     managers = p.slaves.map { case s =>
       TLManagerParameters(
         address            = s.address,
+        resources          = s.resources,
         regionType         = s.regionType,
         executable         = s.executable,
         nodePath           = s.nodePath,