Abstract class for coherence policies
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@ -47,9 +47,7 @@ class ioTileLink extends Bundle {
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val xact_finish = new TransactionFinish().asOutput
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val xact_finish = new TransactionFinish().asOutput
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}
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}
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trait ThreeStateIncoherence {
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trait CoherencePolicy {
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val tileInvalid :: tileClean :: tileDirty :: Nil = Enum(3){ UFix() }
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def cpuCmdToRW( cmd: Bits): (Bool, Bool) = {
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def cpuCmdToRW( cmd: Bits): (Bool, Bool) = {
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val store = (cmd === M_XWR)
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val store = (cmd === M_XWR)
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val load = (cmd === M_XRD)
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val load = (cmd === M_XRD)
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@ -58,6 +56,10 @@ trait ThreeStateIncoherence {
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val write = store || amo || (cmd === M_PFW)
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val write = store || amo || (cmd === M_PFW)
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(read, write)
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(read, write)
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}
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}
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}
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trait ThreeStateIncoherence extends CoherencePolicy {
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val tileInvalid :: tileClean :: tileDirty :: Nil = Enum(3){ UFix() }
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def isHit ( cmd: Bits, state: UFix): Bool = {
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def isHit ( cmd: Bits, state: UFix): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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val (read, write) = cpuCmdToRW(cmd)
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@ -87,32 +89,35 @@ trait ThreeStateIncoherence {
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}
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}
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trait FourStateCoherence {
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trait FourStateCoherence extends CoherencePolicy {
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val tileInvalid :: tileShared :: tileExclusiveClean :: tileExclusiveDirty :: Nil = Enum(4){ UFix() }
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val tileInvalid :: tileShared :: tileExclusiveClean :: tileExclusiveDirty :: Nil = Enum(4){ UFix() }
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val globalInvalid :: globalShared :: globalExclusiveClean :: Nil = Enum(3){ UFix() }
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val globalInvalid :: globalShared :: globalExclusiveClean :: Nil = Enum(3){ UFix() }
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val probeInvalidate :: probeDowngrade :: probeCopy :: Nil = Enum(3){ UFix() }
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val probeInvalidate :: probeDowngrade :: probeCopy :: Nil = Enum(3){ UFix() }
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def isHit ( cmd: Bits, state: UFix): Bool = {
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def isHit ( cmd: Bits, state: UFix): Bool = {
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val is_hit = Bool(false)
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val (read, write) = cpuCmdToRW(cmd)
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switch(cmd) {
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((read && ( state === tileShared || state === tileExclusiveClean || state === tileExclusiveDirty)) ||
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is(M_XRD) {
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(write && (state === tileExclusiveClean || state === tileExclusiveDirty)))
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is_hit := state === tileShared ||
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state === tileExclusiveClean ||
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state === tileExclusiveDirty
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}
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}
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is(M_XWR) {
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is_hit := state === tileExclusiveClean ||
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def isValid (state: UFix): Bool = {
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state === tileExclusiveDirty
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state != tileInvalid
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}
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}
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is_hit
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}
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}
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def needsWriteback (state: UFix): Bool = {
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def needsWriteback (state: UFix): Bool = {
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state === tileExclusiveDirty
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state === tileExclusiveDirty
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}
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}
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def newStateOnWriteback() = tileInvalid
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def newStateOnFlush() = tileInvalid
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// TODO: New funcs as compared to incoherent protocol:
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def newState(cmd: Bits, state: UFix): UFix
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def newStateOnHit(cmd: Bits, state: UFix): UFix
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def newStateOnPrimaryMiss(cmd: Bits): UFix
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def newStateOnSecondaryMiss(cmd: Bits, state: UFix): UFix
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def needsSecondaryXact (cmd: Bits, outstanding: TransactionInit): Bool
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def needsSecondaryXact (cmd: Bits, outstanding: TransactionInit): Bool
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def getMetaUpdateOnProbe (incoming: ProbeRequest): Bits = {
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def getMetaUpdateOnProbe (incoming: ProbeRequest): Bits = {
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