add FPGA test bench
The memory models now support back pressure on the response.
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@ -12,7 +12,7 @@ class mm_dramsim2_t : public mm_t
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public:
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mm_dramsim2_t() : store_inflight(false), store_count(0) {}
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virtual void init(size_t sz);
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virtual void init(size_t sz, int word_size, int line_size);
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virtual bool req_cmd_ready() { return mem->willAcceptTransaction() && !store_inflight; }
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virtual bool req_data_ready() { return mem->willAcceptTransaction() && store_inflight; }
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@ -27,7 +27,8 @@ class mm_dramsim2_t : public mm_t
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uint64_t req_cmd_addr,
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uint64_t req_cmd_tag,
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bool req_data_val,
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void* req_data_bits
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void* req_data_bits,
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bool resp_rdy
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);
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