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add FPGA test bench

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The memory models now support back pressure on the response.
This commit is contained in:
Andrew Waterman
2013-05-02 04:58:43 -07:00
parent d2e1828714
commit cfa86dba4f
11 changed files with 87 additions and 72 deletions
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15
csrc/emulator.cc
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@ -60,17 +60,18 @@ int main(int argc, char** argv)
fprintf(vcdfile, "$upscope $end\n");
}
mm_t* mm = dramsim2 ? (mm_t*)(new mm_dramsim2_t) : (mm_t*)(new mm_magic_t);
mm->init(MEM_SIZE);
if (loadmem)
load_mem(mm->get_data(), loadmem);
// The chisel generated code
Top_t tile;
srand(random_seed);
tile.init(random_seed != 0);
// Instantiate and initialize main memory
mm_t* mm = dramsim2 ? (mm_t*)(new mm_dramsim2_t) : (mm_t*)(new mm_magic_t);
mm->init(MEM_SIZE, tile.Top__io_mem_resp_bits_data.width()/8, LINE_SIZE);
if (loadmem)
load_mem(mm->get_data(), loadmem);
// Instantiate HTIF
htif = new htif_emulator_t(std::vector<std::string>(argv + 1, argv + argc));
int htif_bits = tile.Top__io_host_in_bits.width();
@ -105,7 +106,9 @@ int main(int argc, char** argv)
tile.Top__io_mem_req_cmd_bits_tag.lo_word(),
tile.Top__io_mem_req_data_valid.lo_word(),
&tile.Top__io_mem_req_data_bits_data.values[0]
&tile.Top__io_mem_req_data_bits_data.values[0],
tile.Top__io_mem_resp_ready.to_bool()
);
if (tile.Top__io_host_clk_edge.to_bool())