riscv/rocket-chip
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Cope with changes to AddrMap

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This commit is contained in:
Andrew Waterman 2016-06-03 13:48:43 -07:00
parent a917f554fd
commit cf8be98b2b
1 changed files with 1 additions and 1 deletions
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groundtest/src/main/scala/tracegen.scala
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@ -185,7 +185,7 @@ class TraceGenerator(id: Int)
// Address bag, shared by all cores, taken from module parameters. // Address bag, shared by all cores, taken from module parameters.
// In addition, there is a per-core random selection of extra addresses. // In addition, there is a per-core random selection of extra addresses.
val addrHashMap = p(GlobalAddrHashMap) val addrHashMap = p(GlobalAddrMap)
val baseAddr = addrHashMap("mem").start + 0x01000000 val baseAddr = addrHashMap("mem").start + 0x01000000
val bagOfAddrs = addressBag.map(x => UInt(x, numBitsInWord)) val bagOfAddrs = addressBag.map(x => UInt(x, numBitsInWord))