riscv/rocket-chip
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add STOP_COND to emulator & match vsim PRINTF_COND

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Colin Schmidt 2016-09-09 10:57:10 -07:00 committed by Andrew Waterman
parent 656aa78f7d
commit cf3c6fa277
3 changed files with 6 additions and 1 deletions
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2
csrc/emulator.cc
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@ -15,6 +15,7 @@
extern dtm_t* dtm; extern dtm_t* dtm;
static uint64_t trace_count = 0; static uint64_t trace_count = 0;
bool verbose; bool verbose;
bool done_reset;
void handle_sigterm(int sig) void handle_sigterm(int sig)
{ {
@ -89,6 +90,7 @@ int main(int argc, char** argv)
tile->eval(); tile->eval();
tile->reset = 0; tile->reset = 0;
} }
done_reset = true;
while (!dtm->done() && !tile->io_success && trace_count < max_cycles) { while (!dtm->done() && !tile->io_success && trace_count < max_cycles) {
tile->clk = 0; tile->clk = 0;

1
csrc/verilator.h
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@ -6,6 +6,7 @@
#include <stdio.h> #include <stdio.h>
extern bool verbose; extern bool verbose;
extern bool done_reset;
class VerilatedVcdFILE : public VerilatedVcdFile { class VerilatedVcdFILE : public VerilatedVcdFile {
public: public:

4
emulator/Makefrag-verilator
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@ -49,7 +49,9 @@ verilator/verilator-$(VERILATOR_VERSION).tar.gz:
# Run Verilator to produce a fast binary to emulate this circuit. # Run Verilator to produce a fast binary to emulate this circuit.
VERILATOR := $(INSTALLED_VERILATOR) --cc --exe VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
VERILATOR_FLAGS := --top-module $(MODEL) +define+PRINTF_COND=\$$c\(\"verbose\"\) --assert \ VERILATOR_FLAGS := --top-module $(MODEL) \
+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
+define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
-Wno-STMTDLY --x-assign unique \ -Wno-STMTDLY --x-assign unique \
-I$(base_dir)/vsrc \ -I$(base_dir)/vsrc \
-O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/csrc/verilator.h" -O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/csrc/verilator.h"