riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Support cache->cpu nacks one cycle after request

Browse Source
This commit is contained in:
Andrew Waterman
2011-12-10 00:42:09 -08:00
parent c01e1f1cef
commit ce201559f3
7 changed files with 60 additions and 45 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
rocket/src/main/scala/consts.scala
View File

@ -186,7 +186,8 @@ object Constants
// rocketNBDCacheDM parameters
val CPU_DATA_BITS = 64;
val CPU_TAG_BITS = 5;
val CPU_TAG_BITS = 11;
val DCACHE_TAG_BITS = 1 + CPU_TAG_BITS;
val OFFSET_BITS = 6; // log2(cache line size in bytes)
val NMSHR = 2; // number of primary misses
val NRPQ = 16; // number of secondary misses