riscv/rocket-chip
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client/master -> inner/outer

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This commit is contained in:
Henry Cook 2014-04-29 16:50:07 -07:00
parent 224e286dd3
commit ce056b4b89
3 changed files with 6 additions and 6 deletions
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6
src/main/scala/RocketChip.scala
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@ -69,16 +69,16 @@ class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) ext
val net = Module(new ReferenceChipCrossbarNetwork) val net = Module(new ReferenceChipCrossbarNetwork)
net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end } net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
net.io.masters zip (masterEndpoints.map(_.io.client)) map { case (net, end) => net <> end } net.io.masters zip (masterEndpoints.map(_.io.inner)) map { case (net, end) => net <> end }
masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } } masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
val conv = Module(new MemIOUncachedTileLinkIOConverter(2)) val conv = Module(new MemIOUncachedTileLinkIOConverter(2))
if(ln.nMasters > 1) { if(ln.nMasters > 1) {
val arb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(ln.nMasters)) val arb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(ln.nMasters))
arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache } arb.io.in zip masterEndpoints.map(_.io.outer) map { case (arb, cache) => arb <> cache }
conv.io.uncached <> arb.io.out conv.io.uncached <> arb.io.out
} else { } else {
conv.io.uncached <> masterEndpoints.head.io.master conv.io.uncached <> masterEndpoints.head.io.outer
} }
llc.io.cpu.req_cmd <> Queue(conv.io.mem.req_cmd) llc.io.cpu.req_cmd <> Queue(conv.io.mem.req_cmd)
llc.io.cpu.req_data <> Queue(conv.io.mem.req_data, refill_cycles) llc.io.cpu.req_data <> Queue(conv.io.mem.req_data, refill_cycles)

4
src/main/scala/fpga.scala
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@ -19,11 +19,11 @@ class FPGAOuterMemorySystem(htif_width: Int)(implicit conf: FPGAUncoreConfigurat
val master = Module(new L2CoherenceAgent(0)) val master = Module(new L2CoherenceAgent(0))
val net = Module(new ReferenceChipCrossbarNetwork) val net = Module(new ReferenceChipCrossbarNetwork)
net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end } net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
net.io.masters.head <> master.io.client net.io.masters.head <> master.io.inner
master.io.incoherent zip io.incoherent map { case (m, c) => m := c } master.io.incoherent zip io.incoherent map { case (m, c) => m := c }
val conv = Module(new MemIOUncachedTileLinkIOConverter(2)) val conv = Module(new MemIOUncachedTileLinkIOConverter(2))
conv.io.uncached <> master.io.master conv.io.uncached <> master.io.outer
io.mem.req_cmd <> Queue(conv.io.mem.req_cmd, 2) io.mem.req_cmd <> Queue(conv.io.mem.req_cmd, 2)
io.mem.req_data <> Queue(conv.io.mem.req_data, tl.dataBits/mif.dataBits) io.mem.req_data <> Queue(conv.io.mem.req_data, tl.dataBits/mif.dataBits)
conv.io.mem.resp <> Queue(io.mem.resp) conv.io.mem.resp <> Queue(io.mem.resp)

2
uncore

@ -1 +1 @@
Subproject commit 181a35962b3ed19f8687551568300a0a4039eb11 Subproject commit 01aca66442c06ef48438268ed7c97561ecd2cc4e