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RegisterRouter: correctly create interrupts vector

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This commit is contained in:
Wesley W. Terpstra 2017-09-27 12:27:16 -07:00
parent 0268959c24
commit ce01ab2700
4 changed files with 4 additions and 4 deletions
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2
src/main/scala/amba/ahb/RegisterRouter.scala
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@ -89,7 +89,7 @@ class AHBRegModule[P, B <: AHBRegBundleBase](val params: P, bundleBuilder: => B,
extends LazyModuleImp(router) with HasRegMap extends LazyModuleImp(router) with HasRegMap
{ {
val io = IO(bundleBuilder) val io = IO(bundleBuilder)
val interrupts = if (router.intnode.in.isEmpty) Vec(0, Bool()) else router.intnode.in(0)._1 val interrupts = if (router.intnode.out.isEmpty) Vec(0, Bool()) else router.intnode.out(0)._1
def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*) def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*)
} }

2
src/main/scala/amba/apb/RegisterRouter.scala
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@ -73,7 +73,7 @@ class APBRegModule[P, B <: APBRegBundleBase](val params: P, bundleBuilder: => B,
extends LazyModuleImp(router) with HasRegMap extends LazyModuleImp(router) with HasRegMap
{ {
val io = IO(bundleBuilder) val io = IO(bundleBuilder)
val interrupts = if (router.intnode.in.isEmpty) Vec(0, Bool()) else router.intnode.in(0)._1 val interrupts = if (router.intnode.out.isEmpty) Vec(0, Bool()) else router.intnode.out(0)._1
def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*) def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*)
} }

2
src/main/scala/amba/axi4/RegisterRouter.scala
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@ -100,7 +100,7 @@ class AXI4RegModule[P, B <: AXI4RegBundleBase](val params: P, bundleBuilder: =>
extends LazyModuleImp(router) with HasRegMap extends LazyModuleImp(router) with HasRegMap
{ {
val io = IO(bundleBuilder) val io = IO(bundleBuilder)
val interrupts = if (router.intnode.in.isEmpty) Vec(0, Bool()) else router.intnode.in(0)._1 val interrupts = if (router.intnode.out.isEmpty) Vec(0, Bool()) else router.intnode.out(0)._1
def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*) def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*)
} }

2
src/main/scala/tilelink/RegisterRouter.scala
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@ -105,7 +105,7 @@ class TLRegModule[P, B <: TLRegBundleBase](val params: P, bundleBuilder: => B, r
extends LazyModuleImp(router) with HasRegMap extends LazyModuleImp(router) with HasRegMap
{ {
val io = IO(bundleBuilder) val io = IO(bundleBuilder)
val interrupts = if (router.intnode.in.isEmpty) Vec(0, Bool()) else router.intnode.in(0)._1 val interrupts = if (router.intnode.out.isEmpty) Vec(0, Bool()) else router.intnode.out(0)._1
val address = router.address val address = router.address
def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*) def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*)
} }