From ce01ab2700f5161cd86700ae48f4c0d52430058e Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 27 Sep 2017 12:27:16 -0700 Subject: [PATCH] RegisterRouter: correctly create interrupts vector --- src/main/scala/amba/ahb/RegisterRouter.scala | 2 +- src/main/scala/amba/apb/RegisterRouter.scala | 2 +- src/main/scala/amba/axi4/RegisterRouter.scala | 2 +- src/main/scala/tilelink/RegisterRouter.scala | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/amba/ahb/RegisterRouter.scala b/src/main/scala/amba/ahb/RegisterRouter.scala index edae7f6b..da1960d7 100644 --- a/src/main/scala/amba/ahb/RegisterRouter.scala +++ b/src/main/scala/amba/ahb/RegisterRouter.scala @@ -89,7 +89,7 @@ class AHBRegModule[P, B <: AHBRegBundleBase](val params: P, bundleBuilder: => B, extends LazyModuleImp(router) with HasRegMap { val io = IO(bundleBuilder) - val interrupts = if (router.intnode.in.isEmpty) Vec(0, Bool()) else router.intnode.in(0)._1 + val interrupts = if (router.intnode.out.isEmpty) Vec(0, Bool()) else router.intnode.out(0)._1 def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*) } diff --git a/src/main/scala/amba/apb/RegisterRouter.scala b/src/main/scala/amba/apb/RegisterRouter.scala index ebff2756..f83c38c9 100644 --- a/src/main/scala/amba/apb/RegisterRouter.scala +++ b/src/main/scala/amba/apb/RegisterRouter.scala @@ -73,7 +73,7 @@ class APBRegModule[P, B <: APBRegBundleBase](val params: P, bundleBuilder: => B, extends LazyModuleImp(router) with HasRegMap { val io = IO(bundleBuilder) - val interrupts = if (router.intnode.in.isEmpty) Vec(0, Bool()) else router.intnode.in(0)._1 + val interrupts = if (router.intnode.out.isEmpty) Vec(0, Bool()) else router.intnode.out(0)._1 def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*) } diff --git a/src/main/scala/amba/axi4/RegisterRouter.scala b/src/main/scala/amba/axi4/RegisterRouter.scala index be601889..32d0b1de 100644 --- a/src/main/scala/amba/axi4/RegisterRouter.scala +++ b/src/main/scala/amba/axi4/RegisterRouter.scala @@ -100,7 +100,7 @@ class AXI4RegModule[P, B <: AXI4RegBundleBase](val params: P, bundleBuilder: => extends LazyModuleImp(router) with HasRegMap { val io = IO(bundleBuilder) - val interrupts = if (router.intnode.in.isEmpty) Vec(0, Bool()) else router.intnode.in(0)._1 + val interrupts = if (router.intnode.out.isEmpty) Vec(0, Bool()) else router.intnode.out(0)._1 def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*) } diff --git a/src/main/scala/tilelink/RegisterRouter.scala b/src/main/scala/tilelink/RegisterRouter.scala index bf523af7..dc49e797 100644 --- a/src/main/scala/tilelink/RegisterRouter.scala +++ b/src/main/scala/tilelink/RegisterRouter.scala @@ -105,7 +105,7 @@ class TLRegModule[P, B <: TLRegBundleBase](val params: P, bundleBuilder: => B, r extends LazyModuleImp(router) with HasRegMap { val io = IO(bundleBuilder) - val interrupts = if (router.intnode.in.isEmpty) Vec(0, Bool()) else router.intnode.in(0)._1 + val interrupts = if (router.intnode.out.isEmpty) Vec(0, Bool()) else router.intnode.out(0)._1 val address = router.address def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*) }