riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

debug: whitespace cleanup

Browse Source
This commit is contained in:
Megan Wachs 2017-04-19 14:07:21 -07:00
parent 5934779082
commit cc7f0a5b7a
1 changed files with 1 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/main/scala/rocketchip/DebugTransport.scala
View File

@ -207,7 +207,6 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
dmiReqReg.addr := UInt(0)
dmiReqReg.data := UInt(0)
dmiReqReg.op := UInt(0)
}.otherwise {
dmiReqReg := dmiAccessChain.io.update.bits
dmiReqValidReg := Bool(true)
@ -219,8 +218,6 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
dmiReqValidReg := Bool(false)
}
io.dmi.resp.ready := dmiAccessChain.io.capture.capture
io.dmi.req.valid := dmiReqValidReg