From cc7f0a5b7ae67a008d09c13d9eb32b7166ccb74f Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Wed, 19 Apr 2017 14:07:21 -0700
Subject: [PATCH] debug: whitespace cleanup

---
 src/main/scala/rocketchip/DebugTransport.scala | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/src/main/scala/rocketchip/DebugTransport.scala b/src/main/scala/rocketchip/DebugTransport.scala
index 4cebca2e..85ffe94b 100644
--- a/src/main/scala/rocketchip/DebugTransport.scala
+++ b/src/main/scala/rocketchip/DebugTransport.scala
@@ -202,12 +202,11 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
   when (dmiAccessChain.io.update.valid) {
     when (skipOpReg) {
       // Do Nothing
-    } .elsewhen (downgradeOpReg || (dmiAccessChain.io.update.bits.op === DMIConsts.dmi_OP_NONE)) {
+    }.elsewhen (downgradeOpReg || (dmiAccessChain.io.update.bits.op === DMIConsts.dmi_OP_NONE)) {
       //Do Nothing
       dmiReqReg.addr := UInt(0)
       dmiReqReg.data := UInt(0)
       dmiReqReg.op   := UInt(0)
-
     }.otherwise {
       dmiReqReg := dmiAccessChain.io.update.bits
       dmiReqValidReg := Bool(true)
@@ -219,8 +218,6 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
     dmiReqValidReg := Bool(false)
   }
 
-  
-
   io.dmi.resp.ready := dmiAccessChain.io.capture.capture
   io.dmi.req.valid := dmiReqValidReg