riscv/rocket-chip
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debug: whitespace cleanup

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This commit is contained in:
Megan Wachs 2017-04-19 14:07:21 -07:00
parent 5934779082
commit cc7f0a5b7a
1 changed files with 1 additions and 4 deletions
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3
src/main/scala/rocketchip/DebugTransport.scala
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@ -207,7 +207,6 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
dmiReqReg.addr := UInt(0) dmiReqReg.addr := UInt(0)
dmiReqReg.data := UInt(0) dmiReqReg.data := UInt(0)
dmiReqReg.op := UInt(0) dmiReqReg.op := UInt(0)
}.otherwise { }.otherwise {
dmiReqReg := dmiAccessChain.io.update.bits dmiReqReg := dmiAccessChain.io.update.bits
dmiReqValidReg := Bool(true) dmiReqValidReg := Bool(true)
@ -219,8 +218,6 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
dmiReqValidReg := Bool(false) dmiReqValidReg := Bool(false)
} }
io.dmi.resp.ready := dmiAccessChain.io.capture.capture io.dmi.resp.ready := dmiAccessChain.io.capture.capture
io.dmi.req.valid := dmiReqValidReg io.dmi.req.valid := dmiReqValidReg