riscv/rocket-chip
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bug fix

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This commit is contained in:
Huy Vo 2013-09-19 20:10:56 -07:00
parent cc7783404d
commit cc3dc1bd0f
1 changed files with 1 additions and 1 deletions
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2
uncore/src/main/scala/llc.scala
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@ -466,7 +466,7 @@ class HellaFlowQueue[T <: Data](val entries: Int)(data: => T) extends Module
val ram_addr = Reg(Bits()) val ram_addr = Reg(Bits())
val ram_out_valid = Reg(Bool()) val ram_out_valid = Reg(Bool())
ram_out_valid := Bool(false) ram_out_valid := Bool(false)
when (do_enq) { ram(enq_ptr) := io.enq.bits.toBits } when (do_enq) { ram(enq_ptr) := io.enq.bits }
when (io.deq.ready && (atLeastTwo || !io.deq.valid && !empty)) { when (io.deq.ready && (atLeastTwo || !io.deq.valid && !empty)) {
ram_out_valid := Bool(true) ram_out_valid := Bool(true)
ram_addr := Mux(io.deq.valid, deq_ptr + UInt(1), deq_ptr) ram_addr := Mux(io.deq.valid, deq_ptr + UInt(1), deq_ptr)