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util: exchange resets between AsyncQueue source and sink

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This commit is contained in:
Wesley W. Terpstra 2016-10-06 20:27:34 -07:00
parent 8c7d469a95
commit cb7b16f1a9
2 changed files with 15 additions and 0 deletions
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7
src/main/scala/uncore/tilelink2/Bundles.scala
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@ -226,6 +226,9 @@ final class AsyncBundle[T <: Data](val depth: Int, gen: T) extends Bundle
val ridx = UInt(width = log2Up(depth)+1).flip val ridx = UInt(width = log2Up(depth)+1).flip
val widx = UInt(width = log2Up(depth)+1) val widx = UInt(width = log2Up(depth)+1)
val mem = Vec(depth, gen) val mem = Vec(depth, gen)
val source_reset_n = Bool()
val sink_reset_n = Bool().flip
override def cloneType: this.type = new AsyncBundle(depth, gen).asInstanceOf[this.type] override def cloneType: this.type = new AsyncBundle(depth, gen).asInstanceOf[this.type]
} }
@ -236,6 +239,8 @@ object FromAsyncBundle
x.ridx := sink.io.ridx x.ridx := sink.io.ridx
sink.io.widx := x.widx sink.io.widx := x.widx
sink.io.mem := x.mem sink.io.mem := x.mem
sink.io.source_reset_n := x.source_reset_n
x.sink_reset_n := !sink.reset
val out = Wire(Irrevocable(x.mem(0))) val out = Wire(Irrevocable(x.mem(0)))
out.valid := sink.io.deq.valid out.valid := sink.io.deq.valid
out.bits := sink.io.deq.bits out.bits := sink.io.deq.bits
@ -255,6 +260,8 @@ object ToAsyncBundle
source.io.ridx := out.ridx source.io.ridx := out.ridx
out.mem := source.io.mem out.mem := source.io.mem
out.widx := source.io.widx out.widx := source.io.widx
source.io.sink_reset_n := out.sink_reset_n
out.source_reset_n := !source.reset
out out
} }
} }

8
src/main/scala/util/AsyncQueue.scala
View File

@ -34,6 +34,8 @@ class AsyncQueueSource[T <: Data](gen: T, depth: Int, sync: Int) extends Module
val ridx = UInt(INPUT, width = bits+1) val ridx = UInt(INPUT, width = bits+1)
val widx = UInt(OUTPUT, width = bits+1) val widx = UInt(OUTPUT, width = bits+1)
val mem = Vec(depth, gen).asOutput val mem = Vec(depth, gen).asOutput
// Reset for the other side
val sink_reset_n = Bool().flip()
} }
val mem = Reg(Vec(depth, gen)) //This does NOT need to be asynchronously reset. val mem = Reg(Vec(depth, gen)) //This does NOT need to be asynchronously reset.
@ -43,6 +45,7 @@ class AsyncQueueSource[T <: Data](gen: T, depth: Int, sync: Int) extends Module
val index = if (depth == 1) UInt(0) else io.widx(bits-1, 0) ^ (io.widx(bits, bits) << (bits-1)) val index = if (depth == 1) UInt(0) else io.widx(bits-1, 0) ^ (io.widx(bits, bits) << (bits-1))
when (io.enq.fire() && !reset) { mem(index) := io.enq.bits } when (io.enq.fire() && !reset) { mem(index) := io.enq.bits }
val ready_reg = AsyncResetReg(ready, 0) val ready_reg = AsyncResetReg(ready, 0)
io.enq.ready := ready_reg io.enq.ready := ready_reg
@ -61,6 +64,8 @@ class AsyncQueueSink[T <: Data](gen: T, depth: Int, sync: Int) extends Module {
val ridx = UInt(OUTPUT, width = bits+1) val ridx = UInt(OUTPUT, width = bits+1)
val widx = UInt(INPUT, width = bits+1) val widx = UInt(INPUT, width = bits+1)
val mem = Vec(depth, gen).asInput val mem = Vec(depth, gen).asInput
// Reset for the other side
val source_reset_n = Bool().flip()
} }
val ridx = GrayCounter(bits+1, io.deq.fire()) val ridx = GrayCounter(bits+1, io.deq.fire())
@ -94,6 +99,9 @@ class AsyncQueue[T <: Data](gen: T, depth: Int = 8, sync: Int = 3) extends Cross
sink.clock := io.deq_clock sink.clock := io.deq_clock
sink.reset := io.deq_reset sink.reset := io.deq_reset
source.io.sink_reset_n := !io.deq_reset
sink.io.source_reset_n := !io.enq_reset
source.io.enq <> io.enq source.io.enq <> io.enq
io.deq <> sink.io.deq io.deq <> sink.io.deq