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tilelink2: tie off unused channels

This commit is contained in:
Wesley W. Terpstra 2016-09-04 16:47:18 -07:00
parent 68e64a9859
commit cb54df0a8a
7 changed files with 45 additions and 0 deletions

View File

@ -25,6 +25,13 @@ class TLBuffer(entries: Int = 2, pipe: Boolean = false) extends LazyModule
in .b <> Queue(out.b, entries, pipe)
out.c <> Queue(in .c, entries, pipe)
out.e <> Queue(out.e, entries, pipe)
} else {
in.b.valid := Bool(false)
in.c.ready := Bool(true)
in.e.ready := Bool(true)
out.b.ready := Bool(true)
out.c.valid := Bool(false)
out.e.valid := Bool(false)
}
}
}

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@ -227,6 +227,14 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
out.a.bits := in.a.bits
out.a.bits.source := Cat(in.a.bits.source, aFragnum)
out.a.bits.size := aFrag
// Tie off unused channels
in.b.valid := Bool(false)
in.c.ready := Bool(true)
in.e.ready := Bool(true)
out.b.ready := Bool(true)
out.c.valid := Bool(false)
out.e.valid := Bool(false)
}
}

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@ -68,6 +68,11 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
out.c.valid := in.c.valid
in.c.ready := out.c.ready
out.c.bits := in.c.bits
} else {
in.b.valid := Bool(false)
in.c.ready := Bool(true)
out.b.ready := Bool(true)
out.c.valid := Bool(false)
}
if (bce) {
@ -75,6 +80,9 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
out.e.valid := in.e.valid
in.e.ready := out.e.ready
out.e.bits := in.e.bits
} else {
in.e.ready := Bool(true)
out.e.valid := Bool(false)
}
}
}

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@ -103,5 +103,10 @@ class TLLegacy(implicit val p: Parameters) extends LazyModule with HasTileLinkPa
grant.manager_xact_id := out.d.bits.sink
grant.data := out.d.bits.data
grant.addr_beat := beatCounter
// Tie off unused channels
out.b.ready := Bool(true)
out.c.valid := Bool(false)
out.e.valid := Bool(false)
}
}

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@ -108,6 +108,13 @@ class TLNarrower(innerBeatBytes: Int) extends LazyModule
in.e.ready := out.e.ready
out.e.valid := in.e.valid
out.e.bits := in.e.bits
} else {
in.b.valid := Bool(false)
in.c.ready := Bool(true)
in.e.ready := Bool(true)
out.b.ready := Bool(true)
out.c.valid := Bool(false)
out.e.valid := Bool(false)
}
}
}

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@ -46,6 +46,11 @@ class TLRegisterNode(address: AddressSet, concurrency: Option[Int] = None, beatB
// avoid a Mux on the data bus by manually overriding two fields
d.bits.data := out.bits.data
d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck)
// Tie off unused channels
bundleIn(0).b.valid := Bool(false)
bundleIn(0).c.ready := Bool(true)
bundleIn(0).e.ready := Bool(true)
}
}

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@ -62,5 +62,10 @@ class TLRAM(address: AddressSet, beatBytes: Int = 4) extends LazyModule
mem.write(memAddress, wdata, in.a.bits.mask.toBools)
}
}
// Tie off unused channels
in.b.valid := Bool(false)
in.c.ready := Bool(true)
in.e.ready := Bool(true)
}
}