From cb54df0a8a56d2702c01c63b7803025b41490130 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Sun, 4 Sep 2016 16:47:18 -0700
Subject: [PATCH] tilelink2: tie off unused channels

---
 src/main/scala/uncore/tilelink2/Buffer.scala         | 7 +++++++
 src/main/scala/uncore/tilelink2/Fragmenter.scala     | 8 ++++++++
 src/main/scala/uncore/tilelink2/HintHandler.scala    | 8 ++++++++
 src/main/scala/uncore/tilelink2/Legacy.scala         | 5 +++++
 src/main/scala/uncore/tilelink2/Narrower.scala       | 7 +++++++
 src/main/scala/uncore/tilelink2/RegisterRouter.scala | 5 +++++
 src/main/scala/uncore/tilelink2/SRAM.scala           | 5 +++++
 7 files changed, 45 insertions(+)

diff --git a/src/main/scala/uncore/tilelink2/Buffer.scala b/src/main/scala/uncore/tilelink2/Buffer.scala
index c35a395f..3c9c8456 100644
--- a/src/main/scala/uncore/tilelink2/Buffer.scala
+++ b/src/main/scala/uncore/tilelink2/Buffer.scala
@@ -25,6 +25,13 @@ class TLBuffer(entries: Int = 2, pipe: Boolean = false) extends LazyModule
       in .b <> Queue(out.b, entries, pipe)
       out.c <> Queue(in .c, entries, pipe)
       out.e <> Queue(out.e, entries, pipe)
+    } else {
+      in.b.valid := Bool(false)
+      in.c.ready := Bool(true)
+      in.e.ready := Bool(true)
+      out.b.ready := Bool(true)
+      out.c.valid := Bool(false)
+      out.e.valid := Bool(false)
     }
   }
 }
diff --git a/src/main/scala/uncore/tilelink2/Fragmenter.scala b/src/main/scala/uncore/tilelink2/Fragmenter.scala
index 7d308ae3..c719b875 100644
--- a/src/main/scala/uncore/tilelink2/Fragmenter.scala
+++ b/src/main/scala/uncore/tilelink2/Fragmenter.scala
@@ -227,6 +227,14 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
     out.a.bits := in.a.bits
     out.a.bits.source := Cat(in.a.bits.source, aFragnum)
     out.a.bits.size := aFrag
+
+    // Tie off unused channels
+    in.b.valid := Bool(false)
+    in.c.ready := Bool(true)
+    in.e.ready := Bool(true)
+    out.b.ready := Bool(true)
+    out.c.valid := Bool(false)
+    out.e.valid := Bool(false)
   }
 }
 
diff --git a/src/main/scala/uncore/tilelink2/HintHandler.scala b/src/main/scala/uncore/tilelink2/HintHandler.scala
index edca9f20..ed1c12be 100644
--- a/src/main/scala/uncore/tilelink2/HintHandler.scala
+++ b/src/main/scala/uncore/tilelink2/HintHandler.scala
@@ -68,6 +68,11 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
       out.c.valid := in.c.valid
       in.c.ready := out.c.ready
       out.c.bits := in.c.bits
+    } else {
+      in.b.valid := Bool(false)
+      in.c.ready := Bool(true)
+      out.b.ready := Bool(true)
+      out.c.valid := Bool(false)
     }
 
     if (bce) {
@@ -75,6 +80,9 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
       out.e.valid := in.e.valid
       in.e.ready := out.e.ready
       out.e.bits := in.e.bits
+    } else {
+      in.e.ready := Bool(true)
+      out.e.valid := Bool(false)
     }
   }
 }
diff --git a/src/main/scala/uncore/tilelink2/Legacy.scala b/src/main/scala/uncore/tilelink2/Legacy.scala
index c66f48c6..e4b8b2b2 100644
--- a/src/main/scala/uncore/tilelink2/Legacy.scala
+++ b/src/main/scala/uncore/tilelink2/Legacy.scala
@@ -103,5 +103,10 @@ class TLLegacy(implicit val p: Parameters) extends LazyModule with HasTileLinkPa
     grant.manager_xact_id := out.d.bits.sink
     grant.data            := out.d.bits.data
     grant.addr_beat       := beatCounter
+
+    // Tie off unused channels
+    out.b.ready := Bool(true)
+    out.c.valid := Bool(false)
+    out.e.valid := Bool(false)
   }
 }
diff --git a/src/main/scala/uncore/tilelink2/Narrower.scala b/src/main/scala/uncore/tilelink2/Narrower.scala
index 39e5c092..169dd727 100644
--- a/src/main/scala/uncore/tilelink2/Narrower.scala
+++ b/src/main/scala/uncore/tilelink2/Narrower.scala
@@ -108,6 +108,13 @@ class TLNarrower(innerBeatBytes: Int) extends LazyModule
       in.e.ready := out.e.ready
       out.e.valid := in.e.valid
       out.e.bits := in.e.bits
+    } else {
+      in.b.valid := Bool(false)
+      in.c.ready := Bool(true)
+      in.e.ready := Bool(true)
+      out.b.ready := Bool(true)
+      out.c.valid := Bool(false)
+      out.e.valid := Bool(false)
     }
   }
 }
diff --git a/src/main/scala/uncore/tilelink2/RegisterRouter.scala b/src/main/scala/uncore/tilelink2/RegisterRouter.scala
index 17c473ad..e39788e4 100644
--- a/src/main/scala/uncore/tilelink2/RegisterRouter.scala
+++ b/src/main/scala/uncore/tilelink2/RegisterRouter.scala
@@ -46,6 +46,11 @@ class TLRegisterNode(address: AddressSet, concurrency: Option[Int] = None, beatB
     // avoid a Mux on the data bus by manually overriding two fields
     d.bits.data := out.bits.data
     d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck)
+
+    // Tie off unused channels
+    bundleIn(0).b.valid := Bool(false)
+    bundleIn(0).c.ready := Bool(true)
+    bundleIn(0).e.ready := Bool(true)
   }
 }
 
diff --git a/src/main/scala/uncore/tilelink2/SRAM.scala b/src/main/scala/uncore/tilelink2/SRAM.scala
index b20c6922..28639223 100644
--- a/src/main/scala/uncore/tilelink2/SRAM.scala
+++ b/src/main/scala/uncore/tilelink2/SRAM.scala
@@ -62,5 +62,10 @@ class TLRAM(address: AddressSet, beatBytes: Int = 4) extends LazyModule
         mem.write(memAddress, wdata, in.a.bits.mask.toBools)
       }
     }
+
+    // Tie off unused channels
+    in.b.valid := Bool(false)
+    in.c.ready := Bool(true)
+    in.e.ready := Bool(true)
   }
 }