riscv/rocket-chip
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debug: Fixes in how the SimDTM was hooked up to FESVR

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This commit is contained in:
Megan Wachs 2017-03-28 21:13:45 -07:00
parent ff38ebdf5e
commit ca9a5a1cf7
3 changed files with 12 additions and 12 deletions
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4
csrc/SimDTM.cc
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@ -33,11 +33,11 @@ extern "C" int debug_tick
unsigned char debug_req_ready, unsigned char debug_req_ready,
int* debug_req_bits_addr, int* debug_req_bits_addr,
int* debug_req_bits_op, int* debug_req_bits_op,
long long* debug_req_bits_data, int* debug_req_bits_data,
unsigned char debug_resp_valid, unsigned char debug_resp_valid,
unsigned char* debug_resp_ready, unsigned char* debug_resp_ready,
int debug_resp_bits_resp, int debug_resp_bits_resp,
long long debug_resp_bits_data int debug_resp_bits_data
) )
{ {
if (!dtm) { if (!dtm) {

2
src/main/scala/rocketchip/TestHarness.scala
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@ -70,7 +70,7 @@ class SimDTM(implicit p: Parameters) extends BlackBox {
def connect(tbclk: Clock, tbreset: Bool, dutio: uncore.devices.ClockedDMIIO, tbsuccess: Bool) = { def connect(tbclk: Clock, tbreset: Bool, dutio: uncore.devices.ClockedDMIIO, tbsuccess: Bool) = {
io.clk := tbclk io.clk := tbclk
io.reset := tbreset io.reset := tbreset
dutio <> io.debug dutio.dmi <> io.debug
dutio.dmiClock := tbclk dutio.dmiClock := tbclk
dutio.dmiReset := tbreset dutio.dmiReset := tbreset

18
vsrc/SimDTM.v
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@ -6,12 +6,12 @@ import "DPI-C" function int debug_tick
input bit debug_req_ready, input bit debug_req_ready,
output int debug_req_bits_addr, output int debug_req_bits_addr,
output int debug_req_bits_op, output int debug_req_bits_op,
output longint debug_req_bits_data, output int debug_req_bits_data,
input bit debug_resp_valid, input bit debug_resp_valid,
output bit debug_resp_ready, output bit debug_resp_ready,
input int debug_resp_bits_resp, input int debug_resp_bits_resp,
input longint debug_resp_bits_data input int debug_resp_bits_data
); );
module SimDTM( module SimDTM(
@ -20,14 +20,14 @@ module SimDTM(
output debug_req_valid, output debug_req_valid,
input debug_req_ready, input debug_req_ready,
output [ 4:0] debug_req_bits_addr, output [ 6:0] debug_req_bits_addr,
output [ 1:0] debug_req_bits_op, output [ 1:0] debug_req_bits_op,
output [33:0] debug_req_bits_data, output [31:0] debug_req_bits_data,
input debug_resp_valid, input debug_resp_valid,
output debug_resp_ready, output debug_resp_ready,
input [ 1:0] debug_resp_bits_resp, input [ 1:0] debug_resp_bits_resp,
input [33:0] debug_resp_bits_data, input [31:0] debug_resp_bits_data,
output [31:0] exit output [31:0] exit
); );
@ -37,19 +37,19 @@ module SimDTM(
wire #0.1 __debug_req_ready = debug_req_ready; wire #0.1 __debug_req_ready = debug_req_ready;
wire #0.1 __debug_resp_valid = debug_resp_valid; wire #0.1 __debug_resp_valid = debug_resp_valid;
wire [31:0] #0.1 __debug_resp_bits_resp = {30'b0, debug_resp_bits_resp}; wire [31:0] #0.1 __debug_resp_bits_resp = {30'b0, debug_resp_bits_resp};
wire [63:0] #0.1 __debug_resp_bits_data = {30'b0, debug_resp_bits_data}; wire [31:0] #0.1 __debug_resp_bits_data = debug_resp_bits_data;
bit __debug_req_valid; bit __debug_req_valid;
int __debug_req_bits_addr; int __debug_req_bits_addr;
int __debug_req_bits_op; int __debug_req_bits_op;
longint __debug_req_bits_data; int __debug_req_bits_data;
bit __debug_resp_ready; bit __debug_resp_ready;
int __exit; int __exit;
assign #0.1 debug_req_valid = __debug_req_valid; assign #0.1 debug_req_valid = __debug_req_valid;
assign #0.1 debug_req_bits_addr = __debug_req_bits_addr[4:0]; assign #0.1 debug_req_bits_addr = __debug_req_bits_addr[6:0];
assign #0.1 debug_req_bits_op = __debug_req_bits_op[1:0]; assign #0.1 debug_req_bits_op = __debug_req_bits_op[1:0];
assign #0.1 debug_req_bits_data = __debug_req_bits_data[33:0]; assign #0.1 debug_req_bits_data = __debug_req_bits_data[31:0];
assign #0.1 debug_resp_ready = __debug_resp_ready; assign #0.1 debug_resp_ready = __debug_resp_ready;
assign #0.1 exit = __exit; assign #0.1 exit = __exit;