From ca9a5a1cf74ee02dbc1a8b746d5c136669d060c8 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Tue, 28 Mar 2017 21:13:45 -0700
Subject: [PATCH] debug: Fixes in how the SimDTM was hooked up to FESVR

---
 csrc/SimDTM.cc                              |  4 ++--
 src/main/scala/rocketchip/TestHarness.scala |  2 +-
 vsrc/SimDTM.v                               | 18 +++++++++---------
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/csrc/SimDTM.cc b/csrc/SimDTM.cc
index 2948da4e..0688c0df 100644
--- a/csrc/SimDTM.cc
+++ b/csrc/SimDTM.cc
@@ -33,11 +33,11 @@ extern "C" int debug_tick
   unsigned char  debug_req_ready,
   int*           debug_req_bits_addr,
   int*           debug_req_bits_op,
-  long long*     debug_req_bits_data,
+  int*           debug_req_bits_data,
   unsigned char  debug_resp_valid,
   unsigned char* debug_resp_ready,
   int            debug_resp_bits_resp,
-  long long      debug_resp_bits_data
+  int            debug_resp_bits_data
 )
 {
   if (!dtm) {
diff --git a/src/main/scala/rocketchip/TestHarness.scala b/src/main/scala/rocketchip/TestHarness.scala
index 7470ed87..85ab5ea3 100644
--- a/src/main/scala/rocketchip/TestHarness.scala
+++ b/src/main/scala/rocketchip/TestHarness.scala
@@ -70,7 +70,7 @@ class SimDTM(implicit p: Parameters) extends BlackBox {
   def connect(tbclk: Clock, tbreset: Bool, dutio: uncore.devices.ClockedDMIIO, tbsuccess: Bool) = {
     io.clk := tbclk
     io.reset := tbreset
-    dutio <> io.debug
+    dutio.dmi <> io.debug
     dutio.dmiClock := tbclk
     dutio.dmiReset := tbreset
 
diff --git a/vsrc/SimDTM.v b/vsrc/SimDTM.v
index ca2171be..a5f8c233 100644
--- a/vsrc/SimDTM.v
+++ b/vsrc/SimDTM.v
@@ -6,12 +6,12 @@ import "DPI-C" function int debug_tick
   input  bit     debug_req_ready,
   output int     debug_req_bits_addr,
   output int     debug_req_bits_op,
-  output longint debug_req_bits_data,
+  output int     debug_req_bits_data,
 
   input  bit        debug_resp_valid,
   output bit        debug_resp_ready,
   input  int        debug_resp_bits_resp,
-  input  longint    debug_resp_bits_data
+  input  int        debug_resp_bits_data
 );
 
 module SimDTM(
@@ -20,14 +20,14 @@ module SimDTM(
 
   output        debug_req_valid,
   input         debug_req_ready,
-  output [ 4:0] debug_req_bits_addr,
+  output [ 6:0] debug_req_bits_addr,
   output [ 1:0] debug_req_bits_op,
-  output [33:0] debug_req_bits_data,
+  output [31:0] debug_req_bits_data,
 
   input         debug_resp_valid,
   output        debug_resp_ready,
   input  [ 1:0] debug_resp_bits_resp,
-  input  [33:0] debug_resp_bits_data,
+  input  [31:0] debug_resp_bits_data,
 
   output [31:0] exit
 );
@@ -37,19 +37,19 @@ module SimDTM(
   wire #0.1 __debug_req_ready = debug_req_ready;
   wire #0.1 __debug_resp_valid = debug_resp_valid;
   wire [31:0] #0.1 __debug_resp_bits_resp = {30'b0, debug_resp_bits_resp};
-  wire [63:0] #0.1 __debug_resp_bits_data = {30'b0, debug_resp_bits_data};
+  wire [31:0] #0.1 __debug_resp_bits_data = debug_resp_bits_data;
 
   bit __debug_req_valid;
   int __debug_req_bits_addr;
   int __debug_req_bits_op;
-  longint __debug_req_bits_data;
+  int __debug_req_bits_data;
   bit __debug_resp_ready;
   int __exit;
 
   assign #0.1 debug_req_valid = __debug_req_valid;
-  assign #0.1 debug_req_bits_addr = __debug_req_bits_addr[4:0];
+  assign #0.1 debug_req_bits_addr = __debug_req_bits_addr[6:0];
   assign #0.1 debug_req_bits_op = __debug_req_bits_op[1:0];
-  assign #0.1 debug_req_bits_data = __debug_req_bits_data[33:0];
+  assign #0.1 debug_req_bits_data = __debug_req_bits_data[31:0];
   assign #0.1 debug_resp_ready = __debug_resp_ready;
   assign #0.1 exit = __exit;