riscv/rocket-chip
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dcache: fix a gender inversion bug introduced in #826

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This commit is contained in:
Wesley W. Terpstra 2017-06-28 15:38:21 -07:00
parent 02aa80a958
commit ca3030cba3
1 changed files with 2 additions and 1 deletions
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src/main/scala/rocket/DCache.scala
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@ -83,7 +83,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
}
val q_depth = if (rational) (2 min maxUncachedInFlight-1) else 0
val tl_out_a = if (q_depth == 0) tl_out.a else Queue(tl_out.a, q_depth, flow = true, pipe = true)
val tl_out_a = Wire(tl_out.a)
tl_out.a <> (if (q_depth == 0) tl_out_a else Queue(tl_out_a, q_depth, flow = true, pipe = true))
val s1_valid = Reg(next=io.cpu.req.fire(), init=Bool(false))
val s1_probe = Reg(next=tl_out.b.fire(), init=Bool(false))