From ca3030cba3e507f7d065f35f7ec8b5a1cc05af70 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 28 Jun 2017 15:38:21 -0700 Subject: [PATCH] dcache: fix a gender inversion bug introduced in #826 --- src/main/scala/rocket/DCache.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index 1654d6f3..aa1e255e 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -83,7 +83,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { } val q_depth = if (rational) (2 min maxUncachedInFlight-1) else 0 - val tl_out_a = if (q_depth == 0) tl_out.a else Queue(tl_out.a, q_depth, flow = true, pipe = true) + val tl_out_a = Wire(tl_out.a) + tl_out.a <> (if (q_depth == 0) tl_out_a else Queue(tl_out_a, q_depth, flow = true, pipe = true)) val s1_valid = Reg(next=io.cpu.req.fire(), init=Bool(false)) val s1_probe = Reg(next=tl_out.b.fire(), init=Bool(false))