rocketchip: fix uses of AXI4 Fragmenter

src/main/scala/rocketchip/Configs.scala

@@ -42,7 +42,7 @@ class BasePlatformConfig extends Config((site, here, up) => {
   case ErrorConfig => ErrorConfig(Seq(AddressSet(0x1000, 0xfff)))
   case ExtMem => MasterConfig(base=0x80000000L, size=0x10000000L, beatBytes=8, idBits=4)
   case ExtBus => MasterConfig(base=0x60000000L, size=0x20000000L, beatBytes=8, idBits=4)
-  case ExtIn  => SlaveConfig(beatBytes=8, idBits=8, sourceBits=2)
+  case ExtIn  => SlaveConfig(beatBytes=8, idBits=8, sourceBits=4)
 })
 
 /** Actual elaboratable target Configs */

src/main/scala/rocketchip/Periphery.scala

@@ -238,12 +238,14 @@ trait PeripherySlaveAXI4 extends HasTopLevelNetworks {
     masters = Seq(AXI4MasterParameters(
       id = IdRange(0, 1 << config.idBits))))))
 
+  private val fifoBits = 1
   fsb.node :=
-    TLSourceShrinker(1 << config.sourceBits)(
     TLWidthWidget(config.beatBytes)(
     AXI4ToTL()(
+    AXI4UserYanker(1 << (config.sourceBits - fifoBits - 1))(
     AXI4Fragmenter()(
-    l2FrontendAXI4Node))))
+    AXI4IdIndexer(fifoBits)(
+    l2FrontendAXI4Node)))))
 }
 
 trait PeripherySlaveAXI4Bundle extends HasTopLevelNetworksBundle {

src/main/scala/rocketchip/TestHarness.scala

@@ -53,7 +53,7 @@ class SimAXIMem(channels: Int, forceSize: BigInt = 0)(implicit p: Parameters) ex
 
   for (i <- 0 until channels) {
     val sram = LazyModule(new AXI4RAM(AddressSet(0, size-1), beatBytes = config.beatBytes))
-    sram.node := AXI4Buffer()(AXI4Fragmenter(maxInFlight = 4)(node))
+    sram.node := AXI4Buffer()(AXI4Fragmenter()(node))
   }
 
   lazy val module = new LazyModuleImp(this) {