riscv/rocket-chip
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kill mem stage if fpu nacks in mem stage

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Huy Vo 2012-04-01 17:02:32 -07:00
parent 7f254d9670
commit c9c3bd02bc
1 changed files with 3 additions and 2 deletions
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5
rocket/src/main/scala/ctrl.scala
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@ -699,8 +699,9 @@ class rocketCtrl extends Component
// replay mem stage PC on a DTLB miss or a long-latency writeback // replay mem stage PC on a DTLB miss or a long-latency writeback
val mem_ll_wb = io.dpath.mem_wb || io.dpath.mul_result_val || io.dpath.div_result_val val mem_ll_wb = io.dpath.mem_wb || io.dpath.mul_result_val || io.dpath.div_result_val
val dmem_kill_mem = mem_reg_valid && (io.dtlb_miss || io.dmem.resp_nack) val dmem_kill_mem = mem_reg_valid && (io.dtlb_miss || io.dmem.resp_nack)
val replay_mem = dmem_kill_mem || mem_reg_wen && mem_ll_wb || mem_reg_replay || mem_reg_fp_val && io.fpu.nack_mem val fpu_kill_mem = mem_reg_fp_val && io.fpu.nack_mem
val kill_mem = dmem_kill_mem || mem_reg_wen && mem_ll_wb || take_pc_wb || mem_exception || mem_reg_kill val replay_mem = dmem_kill_mem || mem_reg_wen && mem_ll_wb || mem_reg_replay || fpu_kill_mem
val kill_mem = dmem_kill_mem || mem_reg_wen && mem_ll_wb || take_pc_wb || mem_exception || mem_reg_kill || fpu_kill_mem
val kill_dcache = io.dtlb_miss || mem_reg_wen && mem_ll_wb || take_pc_wb || mem_exception || mem_reg_kill val kill_dcache = io.dtlb_miss || mem_reg_wen && mem_ll_wb || take_pc_wb || mem_exception || mem_reg_kill
// replay execute stage PC when the D$ is blocked, when the D$ misses, // replay execute stage PC when the D$ is blocked, when the D$ misses,